tangxifan
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2facde2097
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[core] reworked fabric generator to use config child type
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2023-08-03 12:57:50 -07:00 |
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tangxifan
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87f2822ef8
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[core] working on logical and physical children
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2023-08-02 19:46:27 -07:00 |
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tangxifan
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da36b735c6
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[core] syntax
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2023-07-24 12:13:45 -07:00 |
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tangxifan
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327f7f4dab
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[core] now adapt to latest API of DeviceGrid
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2023-06-07 18:54:48 -07:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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036933dc14
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[engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols
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2022-09-14 16:46:10 -07:00 |
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tangxifan
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19a551e641
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[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
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2021-10-09 16:44:04 -07:00 |
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tangxifan
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8f5f30792f
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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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2021-10-08 15:25:37 -07:00 |
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tangxifan
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b87b7a99c5
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[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
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2021-09-29 20:21:46 -07:00 |
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tangxifan
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be4c850d2d
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[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
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2021-09-24 12:03:35 -07:00 |
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tangxifan
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7e27c0caf3
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[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
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2021-09-23 16:16:39 -07:00 |
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tangxifan
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7688c0570f
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[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
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2021-09-21 15:08:08 -07:00 |
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tangxifan
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36a4da863c
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[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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tangxifan
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26b1e48723
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[Engine] Merge BL/WLs in the Grid/CB/SB modules
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2021-09-15 11:27:55 -07:00 |
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tangxifan
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4af6413c97
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[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
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2021-09-10 17:03:44 -07:00 |
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tangxifan
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ba1e277dc9
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[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
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2021-09-10 15:05:46 -07:00 |
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tangxifan
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35c7b09888
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[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
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2021-09-09 15:23:29 -07:00 |
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tangxifan
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b787c4e100
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[Engine] Register QL memory bank as a legal protocol
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2021-09-09 15:06:51 -07:00 |
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tangxifan
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ed80d6b3f4
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[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
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2021-09-05 13:23:38 -07:00 |
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tangxifan
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cf2e479d18
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[Engine] Refactor the TopModuleNumConfigBits data structure
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2021-09-05 12:01:38 -07:00 |
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tangxifan
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f75456e304
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[Engine] Update BL/WL estimation function for QL memory bank protocol
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2021-09-05 11:53:33 -07:00 |
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tangxifan
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5759f5f35b
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[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
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2021-09-03 17:55:23 -07:00 |
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tangxifan
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088198c861
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[Tool] enhance error checking in fabric key parser
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2020-11-13 10:56:00 -07:00 |
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tangxifan
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5bcd559851
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[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
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2020-10-30 17:29:04 -06:00 |
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tangxifan
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0d77916041
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[Tool] Support multi-region frame-based configuration protocol
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2020-10-30 10:43:11 -06:00 |
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tangxifan
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8ef6ae32fb
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[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
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2020-10-29 17:35:55 -06:00 |
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tangxifan
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987eccf586
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[Tool] Bug fix in multi-region memory bank; Basic test passed
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2020-10-29 16:26:45 -06:00 |
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tangxifan
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448e88645a
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[Tool] Support multiple memory banks in top-level module
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2020-10-29 12:42:03 -06:00 |
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tangxifan
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bd49ea95d4
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[Tool] Add function to comput configuration bits by region
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2020-10-28 12:37:09 -06:00 |
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tangxifan
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e179a58b15
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[OpenFPGA Tool] Bug fix for long runtime
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2020-09-28 20:42:18 -06:00 |
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tangxifan
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f93d46a870
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[OpenFPGA Tool] Add multiple configuration chain support in top module builder
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2020-09-28 19:03:19 -06:00 |
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tangxifan
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552dddffd0
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[OpenFPGA Tool] Support configurable regions in module manager
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2020-09-28 18:13:07 -06:00 |
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tangxifan
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66e5e141a1
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improve fabric key loader to reduce runtime
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2020-07-07 10:19:34 -06:00 |
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tangxifan
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824b56f14c
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fabric key can now accept instance name only; decoders are no longer part of the key
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2020-07-06 16:42:33 -06:00 |
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tangxifan
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e7d5736269
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add profile time to top module builder for better spot on runtime/memory overhead sources
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2020-06-29 23:17:03 -06:00 |
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tangxifan
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9d32a5b81f
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add alias name support for fabric key
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2020-06-27 14:59:53 -06:00 |
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tangxifan
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a5055e9d26
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add support about loading external fabric key
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2020-06-12 13:03:11 -06:00 |
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tangxifan
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9dbf536306
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add shuffled configurable children support for top module
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2020-06-12 11:16:53 -06:00 |
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tangxifan
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3c10af7f2b
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bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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5368485bd6
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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0e16ee1030
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add configuration bus nets for memory bank decoders at top module
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fa8dfc1fbd
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add configuration protocol ports to top module for memory bank organization
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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b9aac3cbdf
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updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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c696e3d20f
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refine frame-based memory addition to compact the area
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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ed2325ec9e
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add frame decoder build-up to top-level module
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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290dd1a8a6
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add frame decoder builder to all the module graph builder except the top-level
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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63306ce3a0
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add comments to explain the memory organization in the top-level module
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2020-04-01 11:05:30 -06:00 |
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tangxifan
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c855ab24f5
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put build top module memory connections online
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2020-02-14 11:07:04 -07:00 |