Commit Graph

399 Commits

Author SHA1 Message Date
tangxifan 4da5035627 Connect CCFFs in a chain in a Verilog module 2019-09-27 20:50:12 -06:00
tangxifan f0949fea2f Merge branch 'dev' into refactoring 2019-09-27 18:09:58 -06:00
tangxifan 1e187f3d15 start adding memory circuit to Switch blocks 2019-09-27 18:08:37 -06:00
AurelienUoU 640922accd Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-27 16:54:13 -06:00
AurelienUoU a93d7e57f7 Scan chain support in directlist 2019-09-27 16:53:00 -06:00
tangxifan 167778cf57 refactoring MUX Verilog instanciation in Switch block 2019-09-27 16:05:47 -06:00
tangxifan dbe1625267 Refactored Verilog wiring for formal verification ports in Switch Blocks 2019-09-27 13:51:22 -06:00
tangxifan ead014e7d8 refactoring the configuration bus Verilog generation for MUXes 2019-09-27 11:47:34 -06:00
tangxifan 091bbd4d9c start refactoring the num_config_bits for circuit model 2019-09-26 22:53:07 -06:00
tangxifan 8ccf681749 Merge branch 'dev' into refactoring 2019-09-26 21:00:19 -06:00
tangxifan f0589cc2cf refactoring mux Verilog generation for switch blocks 2019-09-26 20:59:19 -06:00
tangxifan 05eaa412b1 refactored short-connection of switch block 2019-09-26 14:31:05 -06:00
AurelienUoU 3b13c959f3 Finish renaming SCFF to CCFF 2019-09-26 14:04:40 -06:00
AurelienUoU c4449b667f Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-26 11:34:59 -06:00
AurelienUoU 056219f180 Rename SCFF to CCFF, configuration chain flip flop 2019-09-26 11:32:57 -06:00
tangxifan ea0da49e04 Merge branch 'dev' into refactoring 2019-09-25 21:06:06 -06:00
tangxifan 5bb40e7f74 refactored local wire generation for Switch block 2019-09-25 21:05:02 -06:00
AurelienUoU e5faeb1400 Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-25 16:50:53 -06:00
AurelienUoU a35e2936b2 Fix verilog generation for direct connexion from directlist 2019-09-25 16:44:00 -06:00
tangxifan 2b0e2615fa refactored sram port addition to module manager 2019-09-25 16:09:58 -06:00
tangxifan c911f15a67 add formal verification port to SB Verilog generation 2019-09-23 21:15:45 -06:00
tangxifan e1742b68ef add pre-processing flag support for module manager 2019-09-23 20:25:53 -06:00
tangxifan d2ddbc19a3 refactoring the reserved sram port generation 2019-09-22 16:38:16 -06:00
tangxifan 2c4372c506 add reserved BLB/WL port naming 2019-09-22 12:16:43 -06:00
tangxifan 1e4177067d remove port size in the module definition 2019-09-22 11:21:43 -06:00
tangxifan 0ff0c8cf06 bug fix for IO=1 2019-09-19 15:43:25 -06:00
tangxifan e0b253d30a minor fix for non-LUT intermedate buffer case 2019-09-18 15:15:03 -06:00
tangxifan 0f0d06aad7 add non-LUT intermediate buffer to test and apply minor bug fix 2019-09-18 15:04:51 -06:00
tangxifan d7ac7d3649 start refactoring the switch block verilog generation 2019-09-17 20:40:26 -06:00
tangxifan 2294aecef2 remove old codes and compact new codes 2019-09-16 20:19:14 -06:00
tangxifan c5ee81541a remove dead codes in routing module generation 2019-09-16 18:47:01 -06:00
tangxifan 0963852091 remove useless global ports for routing channel modules
Need to rework the top-netlist generator before the new module generator can be plugged-in
2019-09-16 18:38:37 -06:00
tangxifan d83cad7c2e refactoring Verilog generation for routing channels 2019-09-16 17:35:51 -06:00
Ganesh Gore ec3854a648 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-14 00:14:17 -06:00
tangxifan f69ce708ca rework on the order of top-level functions 2019-09-13 21:59:52 -06:00
tangxifan 29e80d157c Start developing BitstreamContext 2019-09-13 21:27:47 -06:00
tangxifan e64cfc5852 start refactoring memory decoders 2019-09-13 20:58:55 -06:00
tangxifan d6fc9c1c71 Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later 2019-09-13 15:36:35 -06:00
tangxifan 009c0d63b5 refactored the memory bank. Ready to plug-in the test 2019-09-13 15:05:31 -06:00
tangxifan 99c30fa7dd keep refactoring the memory Verilog generation 2019-09-13 14:02:04 -06:00
tangxifan 56f40cf46c light modification on Verilog Mux generation and start refactoring memory Verilog generation 2019-09-13 12:22:57 -06:00
tangxifan d8b9349066 remove legacy codes 2019-09-13 11:48:25 -06:00
tangxifan b920f0fc38 refactored user template Verilog generation 2019-09-13 11:41:54 -06:00
tangxifan 0e6c88dd52 delete legacy codes for wire Verilog generation 2019-09-12 21:06:53 -06:00
tangxifan c20e182484 plugged in the refactored wire Verilog generation 2019-09-12 20:56:30 -06:00
tangxifan 2b829238b5 refactored wire Verilog generation 2019-09-12 20:49:02 -06:00
tangxifan 79fa858f36 remove unused ports for Verilog modules 2019-09-11 19:39:59 -06:00
tangxifan 2bed51bf29 minor bug fix for echo 2019-09-11 17:41:45 -06:00
tangxifan 0399319212 refactored LUT Verilog generation 2019-09-11 17:04:43 -06:00
tangxifan 6a5b50facf refactored RRAM MUX verilog generation 2019-09-10 20:45:44 -06:00