tangxifan
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462fc0d04e
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add spice transistor wrapper writer
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2020-07-05 14:50:29 -06:00 |
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tangxifan
|
b38ee0e8be
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add spice writer functions
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2020-07-05 13:58:05 -06:00 |
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tangxifan
|
81171a8f97
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start transplanting FPGA-SPICE
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2020-07-05 12:10:12 -06:00 |
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tangxifan
|
1ad6e8292a
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move constants from verilog domain to common so that FPGA-SPICE can share
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2020-07-05 11:39:46 -06:00 |
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tangxifan
|
7c2a0a6ad2
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streamline fabric verilog options
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2020-07-05 11:28:14 -06:00 |
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tangxifan
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83e26adf90
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add module usage types for future FPGA-SPICE development
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2020-07-04 22:33:54 -06:00 |
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tangxifan
|
4f8260a7ba
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remove obselete codes and update regression tests
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2020-07-04 17:31:34 -06:00 |
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tangxifan
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033c92c365
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precisely reserve memory for child blocks in bitstream manager
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2020-07-03 22:47:21 -06:00 |
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tangxifan
|
46f038c829
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bug fix in grid config block allocation
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2020-07-03 20:46:04 -06:00 |
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tangxifan
|
f040fc78a9
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now reserve blocks in bitstream manager can accurately capture the size
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2020-07-03 20:06:12 -06:00 |
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tangxifan
|
8067a13346
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bug fix for memory bank due to encoding bl/wl addresses in fabric bitstream
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2020-07-03 15:56:20 -06:00 |
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tangxifan
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2a9377b3f4
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use encoded address in storage of fabric bitstream to save memory
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2020-07-03 15:12:29 -06:00 |
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tangxifan
|
1f38e17111
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bug fix for naming conflicts in mux local encoder and architecture decoders
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2020-07-03 14:12:13 -06:00 |
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tangxifan
|
70d9678578
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reserve child block in bistream manager
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2020-07-03 14:04:10 -06:00 |
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tangxifan
|
2783fda344
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use index range instead of vector for block bitstream
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2020-07-03 11:42:38 -06:00 |
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tangxifan
|
6ea857ae6c
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use fast method to inquire number of bits and blocks in bitstream databases
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2020-07-03 10:55:25 -06:00 |
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tangxifan
|
7ca1a5bdc1
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Fabric bitstream now allocates vectors in conditions for memory efficiency
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2020-07-03 10:17:03 -06:00 |
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tangxifan
|
8a45e48a1c
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minor fix
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2020-07-02 22:27:48 -06:00 |
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tangxifan
|
246b4d5ac6
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reserve block bits to save memory
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2020-07-02 21:52:32 -06:00 |
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tangxifan
|
dee4be96af
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reserve all the input/output net storage in bitstream manager
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2020-07-02 19:17:34 -06:00 |
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tangxifan
|
f97e3bfba6
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add timer to openfpga shell
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2020-07-02 18:02:33 -06:00 |
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tangxifan
|
81c9fcb7c0
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bug fix when optimizing the fabric bitstream data structure
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2020-07-02 16:41:32 -06:00 |
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tangxifan
|
adee87569d
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enable fast bitstream building by creating a frame view of fabric
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2020-07-02 16:25:36 -06:00 |
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tangxifan
|
9608cefa86
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remove id vector in fabric bitstream database and replace with more memory efficient implementation
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2020-07-02 16:08:50 -06:00 |
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tangxifan
|
9f19c36a89
|
use char in fabric bitstream to save memory footprint
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2020-07-02 15:56:50 -06:00 |
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tangxifan
|
405824081b
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reserve configuration blocks and bits in bitstream manager builder to be memory efficient
|
2020-07-02 15:28:52 -06:00 |
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tangxifan
|
b85af57971
|
optimizing fabric bitsteream memory footprint
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2020-07-02 12:39:18 -06:00 |
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tangxifan
|
ac22ba28e4
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add config protocol type information to simulation ini file
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2020-07-02 12:26:59 -06:00 |
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tangxifan
|
81ecfa3197
|
add comments to clarify how to select CB ports when connecting to SBs at the top level
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2020-07-01 14:44:40 -06:00 |
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tangxifan
|
0a3c746fb1
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now split CB module bus ports into lower/upper parts
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2020-07-01 14:37:13 -06:00 |
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tangxifan
|
cb2baed257
|
bug fix in simulation ini GPIO width
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2020-07-01 13:39:12 -06:00 |
|
tangxifan
|
b74dde919d
|
add additional information in the simulation ini file for UVM
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2020-07-01 13:07:39 -06:00 |
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tangxifan
|
e688ca1388
|
update fabric bitstream writer to support various configuration protocols
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2020-07-01 11:54:28 -06:00 |
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tangxifan
|
1015880d0e
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use easy-to-access net look up in switch block module builder
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2020-06-30 18:15:41 -06:00 |
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tangxifan
|
05187f8aa4
|
use typedef to short the module pin information
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2020-06-30 18:07:22 -06:00 |
|
tangxifan
|
2e7684b746
|
adapt bus ports in connection block module builder
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2020-06-30 17:50:53 -06:00 |
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tangxifan
|
2ef083c49d
|
adapt SB module builder to use bus ports
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2020-06-30 16:02:40 -06:00 |
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tangxifan
|
f023652ac4
|
keep optimizing memory footprint of module manager by using net terminal storage
|
2020-06-30 14:18:05 -06:00 |
|
tangxifan
|
f49cabeeda
|
optimize memory efficiency for module net id storage
|
2020-06-30 11:33:06 -06:00 |
|
tangxifan
|
23bcad0678
|
use more robust net builder in inter tile connections
|
2020-06-30 10:49:17 -06:00 |
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tangxifan
|
025d4a3599
|
use efficient net builder in top module connection builder
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2020-06-29 23:28:26 -06:00 |
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tangxifan
|
e7d5736269
|
add profile time to top module builder for better spot on runtime/memory overhead sources
|
2020-06-29 23:17:03 -06:00 |
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tangxifan
|
57e6c84252
|
add reserve net sources and sinks to module manager
|
2020-06-29 22:49:11 -06:00 |
|
tangxifan
|
66746f69da
|
optimizing memory efficiency by reserving nets in module manager
|
2020-06-29 21:27:43 -06:00 |
|
tangxifan
|
e9937954f2
|
optimizing the constant writing in Verilog for single bits
|
2020-06-29 12:29:25 -06:00 |
|
tangxifan
|
9d32a5b81f
|
add alias name support for fabric key
|
2020-06-27 14:59:53 -06:00 |
|
tangxifan
|
ebf5636e7b
|
add verbose output to edge sorting for GSBs
|
2020-06-26 17:10:51 -06:00 |
|
tangxifan
|
aded675633
|
rename files in fpga bitstream library to be consistent with conventions
|
2020-06-21 13:06:39 -06:00 |
|
tangxifan
|
d526f08782
|
deploy bitstream reader in openfpga shell
|
2020-06-20 18:48:19 -06:00 |
|
tangxifan
|
675a59ecb8
|
Move fpga_bitstream to the libopenfpga library and add XML reader
|
2020-06-20 18:25:17 -06:00 |