tangxifan
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83d6bf32d3
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Merge pull request #59 from LNIS-Projects/dev
Runtime and memory improvement on bitstream database
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2020-07-03 18:32:54 -06:00 |
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tangxifan
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8067a13346
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bug fix for memory bank due to encoding bl/wl addresses in fabric bitstream
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2020-07-03 15:56:20 -06:00 |
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tangxifan
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2a9377b3f4
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use encoded address in storage of fabric bitstream to save memory
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2020-07-03 15:12:29 -06:00 |
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tangxifan
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1f38e17111
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bug fix for naming conflicts in mux local encoder and architecture decoders
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2020-07-03 14:12:13 -06:00 |
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tangxifan
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70d9678578
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reserve child block in bistream manager
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2020-07-03 14:04:10 -06:00 |
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tangxifan
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7d9c36aae1
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use length instead of msb in bitstream manager for block bits to save memory
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2020-07-03 12:06:15 -06:00 |
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tangxifan
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2783fda344
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use index range instead of vector for block bitstream
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2020-07-03 11:42:38 -06:00 |
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tangxifan
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6ea857ae6c
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use fast method to inquire number of bits and blocks in bitstream databases
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2020-07-03 10:55:25 -06:00 |
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tangxifan
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6397cbe9d2
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remove unused data in bitstream manager to compact memory usage
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2020-07-03 10:35:35 -06:00 |
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tangxifan
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7ca1a5bdc1
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Fabric bitstream now allocates vectors in conditions for memory efficiency
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2020-07-03 10:17:03 -06:00 |
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tangxifan
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8a45e48a1c
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minor fix
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2020-07-02 22:27:48 -06:00 |
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tangxifan
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246b4d5ac6
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reserve block bits to save memory
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2020-07-02 21:52:32 -06:00 |
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tangxifan
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043fb54206
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remove unused data in bitstream database
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2020-07-02 20:53:18 -06:00 |
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tangxifan
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9799fea48f
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optimizing bitstream storage
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2020-07-02 19:33:53 -06:00 |
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tangxifan
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dee4be96af
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reserve all the input/output net storage in bitstream manager
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2020-07-02 19:17:34 -06:00 |
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tangxifan
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f97e3bfba6
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add timer to openfpga shell
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2020-07-02 18:02:33 -06:00 |
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tangxifan
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1c634e4600
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add missing task file for generate bitstream test case
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2020-07-02 17:24:51 -06:00 |
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tangxifan
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81c9fcb7c0
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bug fix when optimizing the fabric bitstream data structure
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2020-07-02 16:41:32 -06:00 |
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tangxifan
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adea6fcec4
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add bitstream generation only test case to CI
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2020-07-02 16:31:22 -06:00 |
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tangxifan
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adee87569d
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enable fast bitstream building by creating a frame view of fabric
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2020-07-02 16:25:36 -06:00 |
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tangxifan
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e82d0d9f34
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drop id list in bitstream manager to save memory usage
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2020-07-02 16:18:32 -06:00 |
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tangxifan
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9608cefa86
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remove id vector in fabric bitstream database and replace with more memory efficient implementation
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2020-07-02 16:08:50 -06:00 |
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tangxifan
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9f19c36a89
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use char in fabric bitstream to save memory footprint
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2020-07-02 15:56:50 -06:00 |
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tangxifan
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405824081b
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reserve configuration blocks and bits in bitstream manager builder to be memory efficient
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2020-07-02 15:28:52 -06:00 |
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tangxifan
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b85af57971
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optimizing fabric bitsteream memory footprint
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2020-07-02 12:39:18 -06:00 |
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tangxifan
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ac22ba28e4
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add config protocol type information to simulation ini file
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2020-07-02 12:26:59 -06:00 |
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tangxifan
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06d4667d01
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Merge pull request #58 from LNIS-Projects/dev
Memory, runtime and netlist size optimization
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2020-07-01 17:05:07 -06:00 |
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tangxifan
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81ecfa3197
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add comments to clarify how to select CB ports when connecting to SBs at the top level
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2020-07-01 14:44:40 -06:00 |
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tangxifan
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0a3c746fb1
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now split CB module bus ports into lower/upper parts
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2020-07-01 14:37:13 -06:00 |
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tangxifan
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cb2baed257
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bug fix in simulation ini GPIO width
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2020-07-01 13:39:12 -06:00 |
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tangxifan
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b74dde919d
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add additional information in the simulation ini file for UVM
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2020-07-01 13:07:39 -06:00 |
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tangxifan
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e688ca1388
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update fabric bitstream writer to support various configuration protocols
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2020-07-01 11:54:28 -06:00 |
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tangxifan
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73e75bf456
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add readme for OpenFPGA architecture naming
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2020-07-01 10:27:21 -06:00 |
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tangxifan
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20cf4acda0
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add readme for architecture file naming
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2020-07-01 09:54:13 -06:00 |
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tangxifan
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1015880d0e
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use easy-to-access net look up in switch block module builder
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2020-06-30 18:15:41 -06:00 |
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tangxifan
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05187f8aa4
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use typedef to short the module pin information
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2020-06-30 18:07:22 -06:00 |
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tangxifan
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2e7684b746
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adapt bus ports in connection block module builder
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2020-06-30 17:50:53 -06:00 |
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tangxifan
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2ef083c49d
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adapt SB module builder to use bus ports
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2020-06-30 16:02:40 -06:00 |
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tangxifan
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f023652ac4
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keep optimizing memory footprint of module manager by using net terminal storage
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2020-06-30 14:18:05 -06:00 |
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tangxifan
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f49cabeeda
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optimize memory efficiency for module net id storage
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2020-06-30 11:33:06 -06:00 |
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tangxifan
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23bcad0678
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use more robust net builder in inter tile connections
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2020-06-30 10:49:17 -06:00 |
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tangxifan
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025d4a3599
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use efficient net builder in top module connection builder
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2020-06-29 23:28:26 -06:00 |
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tangxifan
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e7d5736269
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add profile time to top module builder for better spot on runtime/memory overhead sources
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2020-06-29 23:17:03 -06:00 |
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tangxifan
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57e6c84252
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add reserve net sources and sinks to module manager
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2020-06-29 22:49:11 -06:00 |
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tangxifan
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66746f69da
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optimizing memory efficiency by reserving nets in module manager
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2020-06-29 21:27:43 -06:00 |
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tangxifan
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e9937954f2
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optimizing the constant writing in Verilog for single bits
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2020-06-29 12:29:25 -06:00 |
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tangxifan
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933801cfa7
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update documentation about alias support in fabric key
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2020-06-27 15:04:04 -06:00 |
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tangxifan
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b2fb5f760c
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update sample key
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2020-06-27 15:01:12 -06:00 |
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tangxifan
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9d32a5b81f
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add alias name support for fabric key
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2020-06-27 14:59:53 -06:00 |
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tangxifan
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ebf5636e7b
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add verbose output to edge sorting for GSBs
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2020-06-26 17:10:51 -06:00 |