tangxifan
|
c87dbc4880
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start using counter benchmark in regression tests
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
f73dfa2bcc
|
bug fixed in k6_n10_40 architecture
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
0b9971cb5c
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try to deploy the memory bank protocol test case to CI
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
3c10af7f2b
|
bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
baa2c6b7ef
|
update arch to support reset signal for SRAm
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2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
8267dad8ef
|
add decoder support for Z signals
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2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
aac2e8c805
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update openfpga architecture for memory bank usage
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2020-06-11 19:31:14 -06:00 |
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tangxifan
|
82b04ae3f0
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add SRAM verilog for memory bank usage
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2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
5368485bd6
|
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
c85ccceac7
|
try bug fixing in memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
b191732d32
|
show vvp version in CI
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
dda6fe19ae
|
show iverilog version in CI
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
b9dd47d465
|
update documentation about memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
e46651e0c1
|
deploy preconfig regression test for memory bank to CI
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
3f9afea3e8
|
add preconfig testbench test case for memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
03e56f5ca6
|
deploy memory bank regression tests to CI
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
288294c23a
|
add fast configuration test case for memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
73d4c835b7
|
add regression test case for memory bank
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2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
0bee70bee6
|
finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
a1ec6833c2
|
add memory bank example arch xml
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
e14c39e14c
|
update Verilog full testbench generation to support memory bank configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
51e1559352
|
add fabric bitstream support for memory bank configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
0e16ee1030
|
add configuration bus nets for memory bank decoders at top module
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
fa8dfc1fbd
|
add configuration protocol ports to top module for memory bank organization
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
c00653961e
|
minor format fix in documentation
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
ad7422359d
|
deploy compact constant values in Verilog codes
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
0931eccbf6
|
update documentation for the fast configuration options
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
fe2ba7d50a
|
update documentation for standalone configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
c456ef4d00
|
deploy the standalone preconfig testcase to CI
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
2def059b5b
|
add standalone configuration protocol to pre config test cases
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
1fedd00912
|
deploy the flatten configuration memory testcase to CI
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8ec8ac4118
|
bug fixed in flatten memory organization. Passed verification
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
5f6a790eff
|
add new test cases for the standalone memory configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8b5b221a21
|
add new architecture for standalone memory organization
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
b9aac3cbdf
|
updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
fbe05963e0
|
add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
d2d443a988
|
start developing memory bank and standalone configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
9a6a5e3310
|
deploy fast configuration testcase to CI
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
9e176b8d38
|
add fast configuration stats to log
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
a5138113e4
|
add fast configuration testcase
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8b3e79766c
|
add fast configuration option to fpga_verilog to speed up full testbench simulation
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
22648cdb9c
|
deploy the preconfig testbench cases to CI
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
05aa166a9e
|
add preconfig testbench cases to regression tests for different configuration protocols
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
827e2e6713
|
file moving in regression tests
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
de07712a3a
|
update documentation about the frame-based configuration protocol
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
cdc2237008
|
deploy frame-based configuration protocol to travis CI
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
b5e5182f52
|
frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
583c15131b
|
change configuration latch to be triggered at negative edge; Frame-based fabric passed Modelsim verification but failed in iVerilog
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
31c9a011dd
|
keep bug fixing for arch decoders
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
b8c449d520
|
add comments for decoding functions to help debugging the frame-based decoders
|
2020-06-11 19:31:11 -06:00 |