riscv
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OpenFPGA
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show vvp version in CI

This commit is contained in:
tangxifan 2020-05-30 22:29:40 -06:00
parent dda6fe19ae
commit b191732d32
2 changed files with 3 additions and 2 deletions
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1
.travis/install.sh
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@ -33,6 +33,7 @@ set -e
# echo ${PATH}
#fi
iverilog -V
vvp -V
#cd -

4
.travis/script.sh
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@ -58,8 +58,8 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fas
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_frame --debug --show_thread_logs
echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/memory_bank --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_memory_bank --debug --show_thread_logs
#python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/memory_bank --debug --show_thread_logs
#python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_memory_bank --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/memory_bank --debug --show_thread_logs