Baudouin Chauviere
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33e50bbc8c
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fix
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2019-10-01 16:54:16 -06:00 |
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Baudouin Chauviere
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7c3ab38410
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Hot fix
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2019-10-01 16:40:16 -06:00 |
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Baudouin Chauviere
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633a12ee08
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Buggy version but need help on debugging
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2019-10-01 14:49:42 -06:00 |
AurelienUoU
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36f7624b95
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Point to point truth table typo fix
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2019-10-01 13:07:27 -06:00 |
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AurelienUoU
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e2867019e1
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Typo fixing
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2019-09-30 10:38:02 -06:00 |
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AurelienUoU
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74f7a3cfb2
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Doc fixing
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2019-09-30 10:29:42 -06:00 |
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AurelienUoU
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fdc3c5e4a9
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-30 10:02:11 -06:00 |
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AurelienUoU
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5ac79f4805
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Point to point documentation
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2019-09-30 10:00:46 -06:00 |
tangxifan
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b082e60c10
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start refactoring instanciation of memory modules
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2019-09-29 18:20:56 -06:00 |
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tangxifan
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3726e691f4
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simplify the local wire generation for ccffs
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2019-09-28 21:36:56 -06:00 |
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tangxifan
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1983e56557
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make local configuration bus generation more general
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2019-09-28 21:02:14 -06:00 |
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tangxifan
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433fc73460
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refactored local encoder support for Verilog MUX generation
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2019-09-27 23:10:43 -06:00 |
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tangxifan
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4da5035627
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Connect CCFFs in a chain in a Verilog module
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2019-09-27 20:50:12 -06:00 |
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tangxifan
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f0949fea2f
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Merge branch 'dev' into refactoring
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2019-09-27 18:09:58 -06:00 |
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tangxifan
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1e187f3d15
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start adding memory circuit to Switch blocks
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2019-09-27 18:08:37 -06:00 |
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AurelienUoU
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640922accd
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-27 16:54:13 -06:00 |
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AurelienUoU
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a93d7e57f7
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Scan chain support in directlist
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2019-09-27 16:53:00 -06:00 |
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tangxifan
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167778cf57
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refactoring MUX Verilog instanciation in Switch block
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2019-09-27 16:05:47 -06:00 |
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tangxifan
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dbe1625267
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Refactored Verilog wiring for formal verification ports in Switch Blocks
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2019-09-27 13:51:22 -06:00 |
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tangxifan
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ead014e7d8
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refactoring the configuration bus Verilog generation for MUXes
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2019-09-27 11:47:34 -06:00 |
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tangxifan
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091bbd4d9c
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start refactoring the num_config_bits for circuit model
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2019-09-26 22:53:07 -06:00 |
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tangxifan
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8ccf681749
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Merge branch 'dev' into refactoring
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2019-09-26 21:00:19 -06:00 |
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tangxifan
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f0589cc2cf
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refactoring mux Verilog generation for switch blocks
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2019-09-26 20:59:19 -06:00 |
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tangxifan
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05eaa412b1
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refactored short-connection of switch block
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2019-09-26 14:31:05 -06:00 |
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AurelienUoU
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3b13c959f3
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Finish renaming SCFF to CCFF
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2019-09-26 14:04:40 -06:00 |
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AurelienUoU
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c4449b667f
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-26 11:34:59 -06:00 |
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AurelienUoU
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056219f180
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Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
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tangxifan
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ea0da49e04
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Merge branch 'dev' into refactoring
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2019-09-25 21:06:06 -06:00 |
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tangxifan
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5bb40e7f74
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refactored local wire generation for Switch block
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2019-09-25 21:05:02 -06:00 |
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AurelienUoU
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e5faeb1400
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-25 16:50:53 -06:00 |
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AurelienUoU
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a35e2936b2
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Fix verilog generation for direct connexion from directlist
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2019-09-25 16:44:00 -06:00 |
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tangxifan
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2b0e2615fa
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refactored sram port addition to module manager
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2019-09-25 16:09:58 -06:00 |
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tangxifan
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c911f15a67
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add formal verification port to SB Verilog generation
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2019-09-23 21:15:45 -06:00 |
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tangxifan
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e1742b68ef
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add pre-processing flag support for module manager
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2019-09-23 20:25:53 -06:00 |
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AurelienUoU
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feddcbcb21
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-23 11:41:38 -06:00 |
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tangxifan
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d2ddbc19a3
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refactoring the reserved sram port generation
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2019-09-22 16:38:16 -06:00 |
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tangxifan
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8b3de892ef
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simplify the regression test commands
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2019-09-22 12:18:44 -06:00 |
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tangxifan
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2c4372c506
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add reserved BLB/WL port naming
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2019-09-22 12:16:43 -06:00 |
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tangxifan
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1e4177067d
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remove port size in the module definition
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2019-09-22 11:21:43 -06:00 |
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tangxifan
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5efea159c5
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Simplify part of regression test to min_route_chan_width
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2019-09-22 11:14:33 -06:00 |
Ganesh Gore
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1dffe54807
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-22 00:21:25 -06:00 |
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Ganesh Gore
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50039a4b6e
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Added remove run directory option
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2019-09-21 23:35:56 -06:00 |
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AurelienUoU
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cc0bfdd548
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Add testcase in regression test for architecture with 1 IO cell/IO block
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2019-09-20 10:27:26 -06:00 |
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tangxifan
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0ff0c8cf06
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bug fix for IO=1
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2019-09-19 15:43:25 -06:00 |
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tangxifan
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4e7af5cdc5
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update tileable_routing test
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2019-09-18 15:59:32 -06:00 |
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tangxifan
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e0b253d30a
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minor fix for non-LUT intermedate buffer case
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2019-09-18 15:15:03 -06:00 |
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tangxifan
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0f0d06aad7
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add non-LUT intermediate buffer to test and apply minor bug fix
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2019-09-18 15:04:51 -06:00 |
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Ganesh Gore
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8afcba2c45
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-18 12:15:42 -06:00 |
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Ganesh Gore
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cd5fd6ce6c
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Added explicit checking to VVP execution
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2019-09-18 12:14:26 -06:00 |
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Ganesh Gore
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56c40ca06d
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-17 22:12:11 -06:00 |