tangxifan
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49bfb3223c
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add compact routing to regression test
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2019-11-01 10:53:47 -06:00 |
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tangxifan
|
531cc064fc
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bug fixing for formal top-level testbench
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2019-11-01 10:47:40 -06:00 |
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tangxifan
|
d709868463
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adding more regression tests which is quick run but very helpful for debugging
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2019-10-31 20:17:40 -06:00 |
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tangxifan
|
a6a3e7c36b
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adding mcnc_big20 to regression test
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2019-10-31 19:31:27 -06:00 |
|
tangxifan
|
5531422186
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update regression test with no-explicit port mapping cases
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2019-10-30 19:37:06 -06:00 |
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tangxifan
|
55fbd72293
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many bugs have been fixed
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2019-10-30 15:50:42 -06:00 |
|
tangxifan
|
4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
|
10491c4291
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bring single mode test case online with bug fixing
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2019-10-28 17:04:10 -06:00 |
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tangxifan
|
5cb3717433
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add single mode test case to regression test. debugging now
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2019-10-28 15:57:17 -06:00 |
Baudouin Chauviere
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027272c976
|
Faster regression test
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2019-10-05 12:10:55 -06:00 |
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Baudouin Chauviere
|
db059af8b8
|
Lighten the regression test
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2019-10-03 13:33:28 -06:00 |
|
Baudouin Chauviere
|
c7e1f7d90b
|
Added explicit_verilog to regression test in a clean way
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2019-10-03 10:17:04 -06:00 |
|
Baudouin Chauviere
|
33e50bbc8c
|
fix
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2019-10-01 16:54:16 -06:00 |
|
Baudouin Chauviere
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7c3ab38410
|
Hot fix
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2019-10-01 16:40:16 -06:00 |
AurelienUoU
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feddcbcb21
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-23 11:41:38 -06:00 |
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tangxifan
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5efea159c5
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Simplify part of regression test to min_route_chan_width
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2019-09-22 11:14:33 -06:00 |
Ganesh Gore
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1dffe54807
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-22 00:21:25 -06:00 |
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Ganesh Gore
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50039a4b6e
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Added remove run directory option
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2019-09-21 23:35:56 -06:00 |
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AurelienUoU
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cc0bfdd548
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Add testcase in regression test for architecture with 1 IO cell/IO block
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2019-09-20 10:27:26 -06:00 |
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tangxifan
|
4e7af5cdc5
|
update tileable_routing test
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2019-09-18 15:59:32 -06:00 |
|
tangxifan
|
0f0d06aad7
|
add non-LUT intermediate buffer to test and apply minor bug fix
|
2019-09-18 15:04:51 -06:00 |
|
Ganesh Gore
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8afcba2c45
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-18 12:15:42 -06:00 |
|
Ganesh Gore
|
cd5fd6ce6c
|
Added explicit checking to VVP execution
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2019-09-18 12:14:26 -06:00 |
|
Ganesh Gore
|
56c40ca06d
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-17 22:12:11 -06:00 |
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Ganesh Gore
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169732ccc1
|
Added verbose option in VVP output
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2019-09-17 22:09:37 -06:00 |
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tangxifan
|
d7ac7d3649
|
start refactoring the switch block verilog generation
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2019-09-17 20:40:26 -06:00 |
|
Ganesh Gore
|
7be83235a0
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-16 21:25:26 -06:00 |
|
Ganesh Gore
|
678e3181ba
|
Made compact_routing_hierarchy options uncond
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2019-09-16 21:22:13 -06:00 |
|
tangxifan
|
5abbfd6a0f
|
add tileable routing to regression test
|
2019-09-16 20:45:02 -06:00 |
|
Ganesh Gore
|
81b9c5b266
|
Added flag for VVP exit code
|
2019-09-14 12:35:47 -06:00 |
|
Ganesh Gore
|
d90329678a
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-09-14 12:11:36 -06:00 |
|
Ganesh Gore
|
ec3854a648
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-14 00:14:17 -06:00 |
|
Ganesh Gore
|
e5c99c8b12
|
Quick terminate on fail added
|
2019-09-13 23:56:38 -06:00 |
|
Ganesh Gore
|
bd9e57bc37
|
Added better task name
|
2019-09-13 23:30:42 -06:00 |
|
Ganesh Gore
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a6e592247e
|
Replaced options exit_on fail and show_thread logs
|
2019-09-13 22:50:20 -06:00 |
|
Ganesh Gore
|
d64bb18346
|
Separated Modelsim tcl script generation
|
2019-09-07 12:36:22 -04:00 |
|
Ganesh Gore
|
d55b7e9497
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-06 11:49:38 -04:00 |
|
Ganesh Gore
|
bcbcd463fe
|
Added pending runs in log
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2019-09-06 11:48:13 -04:00 |
|
Ganesh Gore
|
9abc1e1e7d
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-05 13:12:41 -04:00 |
|
Ganesh Gore
|
702a7683a8
|
Ensure strict exit of fpga_flow on error
|
2019-09-05 10:23:35 -06:00 |
|
tangxifan
|
d2d750a15c
|
debugged rram mux branch Verilog generation
|
2019-09-02 16:21:29 -06:00 |
|
Ganesh Gore
|
48ec1eefcd
|
Added fpga_task cmd options in doc [ci skip]
|
2019-09-02 02:45:05 -06:00 |
|
Ganesh Gore
|
e37ac1a565
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-02 00:19:19 -06:00 |
|
Ganesh Gore
|
241b001282
|
Added openfpga_task doc
|
2019-09-01 22:15:53 -06:00 |
|
Ganesh Gore
|
ad4c688206
|
Added print for JobID to architecture mapping
|
2019-08-31 22:04:57 -06:00 |
|
Ganesh Gore
|
f4e99c150a
|
resolve missing variable bug
|
2019-08-31 21:55:32 -06:00 |
|
Ganesh Gore
|
3d4f7f66fd
|
Updated to run with python3
|
2019-08-31 21:42:31 -06:00 |
|
Ganesh Gore
|
06c0dbb328
|
Added docuementation for fpga_flow
|
2019-08-31 15:19:34 -06:00 |
|
Ganesh Gore
|
02137805c7
|
Added python version check in flow and task scripts
|
2019-08-29 22:14:30 -06:00 |
|
Ganesh Gore
|
a25124b58c
|
Added additional PATH variables
|
2019-08-29 21:37:07 -06:00 |