tangxifan
|
9bf0e772a3
|
[Regression Tests]Add a new testcase for routing multiplexer designs without buffers
|
2020-09-14 15:45:35 -06:00 |
|
tangxifan
|
7a2502ddf9
|
[documentation] add more guidelines about the vpr-openfpga architecture annotation
|
2020-09-02 22:47:14 -06:00 |
|
tangxifan
|
04070fd4ca
|
[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
|
2020-09-02 22:16:10 -06:00 |
|
tangxifan
|
b5251ce5af
|
[documentation] update motivation figure and layout licenses
|
2020-09-01 11:07:50 -06:00 |
|
tangxifan
|
4b3142c4ee
|
[Architecture File] Patch openfpga architecture with default circuit model definition
|
2020-08-23 15:13:28 -06:00 |
|
tangxifan
|
9101ba1021
|
[Architecture Language] Update openfpga architecture files for default models
|
2020-08-23 14:55:44 -06:00 |
|
tangxifan
|
ac8e937a50
|
[Documentation] Update for default circuit model rules
|
2020-08-23 14:08:38 -06:00 |
|
tangxifan
|
9c66a35bf6
|
[arch language] Now circuit library will automatically identify the default circuit model if needed
|
2020-08-23 14:06:03 -06:00 |
|
tangxifan
|
b83319bf14
|
[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
|
2020-08-23 13:48:22 -06:00 |
|
tangxifan
|
fb5a5a2448
|
[documentation] remove the limitation on through channels
|
2020-08-19 20:12:49 -06:00 |
|
tangxifan
|
6c925dcded
|
[regression test] Add more tests for thru channels and deploy to CI
|
2020-08-19 20:11:37 -06:00 |
|
tangxifan
|
1a3e020174
|
deploy through channel test case to CI
|
2020-08-19 20:04:01 -06:00 |
|
tangxifan
|
8041c90f12
|
bug fix in through channel support in tileable routing
|
2020-08-19 20:01:50 -06:00 |
|
tangxifan
|
881672d46a
|
update thru channel arch for avoid buggy pin locations
|
2020-08-19 19:52:35 -06:00 |
|
tangxifan
|
47f15729ad
|
update doc about the limitation on using tileable routing
|
2020-08-19 18:37:28 -06:00 |
|
tangxifan
|
d6d17675e2
|
update docoumentation about the constraints when using tileable rr_graph generator
|
2020-08-19 18:01:32 -06:00 |
|
tangxifan
|
bf08e1841c
|
add new test case using thru channels
|
2020-08-19 17:58:34 -06:00 |
|
tangxifan
|
f3ca1c0973
|
fix rr_graph on thru routing channel support
|
2020-08-19 17:28:25 -06:00 |
|
tangxifan
|
f0bc6f83f1
|
disable buffer absorbing in the template script for bitstream generation. This is applicable to a wide range of benchmarks
|
2020-08-19 15:34:59 -06:00 |
|
tangxifan
|
18735894f9
|
bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2
|
2020-08-19 15:27:30 -06:00 |
|
tangxifan
|
3273f441fe
|
bug fix in the flagship vpr arch
|
2020-08-19 15:23:20 -06:00 |
|
tangxifan
|
aa4a9b28cc
|
start testing the initial offset in the flagship architecture
|
2020-08-19 15:03:46 -06:00 |
|
tangxifan
|
161d660837
|
update documentation for the initial offset when mapping physical pins
|
2020-08-19 15:00:46 -06:00 |
|
tangxifan
|
3eea12ceae
|
added a new XML syntax: initial offset for physical mode pin mapping
|
2020-08-19 14:43:44 -06:00 |
|
tangxifan
|
f631245b2b
|
bug fix and enriched debugging info print out
|
2020-08-19 13:41:04 -06:00 |
|
tangxifan
|
79b6ff3cb0
|
relax checking for device annotation as we support multi-port during physical mode pin mapping
|
2020-08-19 12:44:51 -06:00 |
|
tangxifan
|
f64079641d
|
bug fix in flagship vpr arch with frac mem and dsp
|
2020-08-19 12:43:58 -06:00 |
|
tangxifan
|
af1c7c6f29
|
start fixing the bug in thru channels
|
2020-08-19 12:18:35 -06:00 |
|
tangxifan
|
d7efdf35b6
|
add custom pin location to the flagship vpr arch with frac mem and dsp
|
2020-08-19 11:15:25 -06:00 |
|
tangxifan
|
dbd93e429d
|
now pro_blif.pl can accept customized clock name
|
2020-08-19 09:43:44 -06:00 |
|
tangxifan
|
743167521a
|
add Verilog design for fracturable 32k memory
|
2020-08-18 21:13:46 -06:00 |
|
tangxifan
|
42b5ea2cb1
|
bug fix in openfpga arch for frac mem and dsp
|
2020-08-18 20:42:36 -06:00 |
|
tangxifan
|
3ee4e10aa8
|
bug fix in the frac mem & DSP vpr arch
|
2020-08-18 17:25:45 -06:00 |
|
tangxifan
|
098859fe06
|
bug fix in the frac memory & DSP architecture
|
2020-08-18 15:05:51 -06:00 |
|
tangxifan
|
21c7eaa9cf
|
add 36-bit fracturable multiplier Verilog
|
2020-08-18 14:06:08 -06:00 |
|
tangxifan
|
53f87f44b4
|
update documentation for the multi-port support in physical pb_pin
|
2020-08-18 12:44:38 -06:00 |
|
tangxifan
|
2712c354a9
|
now physical pb_port binding support multiple ports
|
2020-08-18 12:38:56 -06:00 |
|
tangxifan
|
f833e0ec66
|
add a flagship architecture using fracturable memory and dsp
|
2020-08-17 17:49:51 -06:00 |
|
tangxifan
|
cfd035bf8f
|
update tutorials about the verilog-to-verification
|
2020-08-17 14:33:51 -06:00 |
|
tangxifan
|
1ca2829868
|
update readme for vpr architecture naming
|
2020-08-17 13:54:26 -06:00 |
|
tangxifan
|
cadf29022e
|
add README to explain the organization of regression tests
|
2020-07-28 13:44:06 -06:00 |
|
tangxifan
|
1e53d79c57
|
deploy large bitstream regression tests to CI
|
2020-07-28 12:41:58 -06:00 |
|
tangxifan
|
f33422d4d7
|
add regression test to track runtime on big fpga devices using practical benchmarks
|
2020-07-28 12:38:42 -06:00 |
|
tangxifan
|
534c609e17
|
add fixed layouts to a flagship architecture to test bitstream generation runtime
|
2020-07-28 11:51:50 -06:00 |
|
tangxifan
|
a156807559
|
enrich basic regression tests to cover more critical microbenchmarks
|
2020-07-27 19:47:43 -06:00 |
|
tangxifan
|
9809db01c5
|
deploy load_arch_bitstream test case to CI
|
2020-07-27 19:39:14 -06:00 |
|
tangxifan
|
5d83abb2cf
|
bug fix in read architecture bitstream and regression tests
|
2020-07-27 19:37:05 -06:00 |
|
tangxifan
|
9a7364c6e6
|
bug fix in fabric bitstream XML syntax
|
2020-07-27 19:22:36 -06:00 |
|
tangxifan
|
31e7a753a6
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-07-27 19:22:16 -06:00 |
ganeshgore
|
747c062f86
|
BugFix : Flow script accepts extra OpenFPGA arguments
|
2020-07-27 18:10:43 -06:00 |