tangxifan
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0d5292ad0d
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adapt verilog writer utils
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2020-02-15 23:26:59 -07:00 |
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tangxifan
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bf54be3d00
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add option data structure for FPGA Verilog
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2020-02-15 21:39:47 -07:00 |
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tangxifan
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da79ef687c
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add missing files
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2020-02-15 20:54:37 -07:00 |
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tangxifan
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8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
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622c7826d1
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start transplanting fpga_verilog
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2020-02-15 15:03:00 -07:00 |
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tangxifan
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85627dc128
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put build top module online
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2020-02-15 14:13:32 -07:00 |
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tangxifan
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539f13720a
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tile direct supports inter-column/inter-row direct connections
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2020-02-15 13:42:53 -07:00 |
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tangxifan
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213c611c0b
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add tile direct builder
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2020-02-14 22:21:32 -07:00 |
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tangxifan
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7e86cf1079
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add tile direct data structure
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2020-02-14 19:11:49 -07:00 |
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tangxifan
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59c13550e0
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add direct annotation with inter-column/row syntax
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2020-02-14 17:40:59 -07:00 |
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tangxifan
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c855ab24f5
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put build top module memory connections online
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2020-02-14 11:07:04 -07:00 |
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tangxifan
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9dc9c2c9f7
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add build top module connection functions
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2020-02-14 10:45:24 -07:00 |
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tangxifan
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36179b6ced
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start moving top-module builder. Now adapt the utils
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2020-02-14 10:00:24 -07:00 |
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tangxifan
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afe8278670
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put routing module builder online
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2020-02-13 17:35:29 -07:00 |
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tangxifan
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cf440f92d3
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put routing module builder util function online
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2020-02-13 16:05:23 -07:00 |
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tangxifan
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89086ed080
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add verbose output to build grid module
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2020-02-13 15:38:26 -07:00 |
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tangxifan
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072965cd64
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make grid module builder online; basic support on physical tiles
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2020-02-13 15:27:16 -07:00 |
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tangxifan
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59d579425e
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add utils for duplicate pins in grid module builder
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2020-02-12 20:48:07 -07:00 |
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tangxifan
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895d5b5a0a
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add utils for grid module builder
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2020-02-12 20:25:05 -07:00 |
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tangxifan
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002c2795fe
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add memory module builder
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2020-02-12 20:06:38 -07:00 |
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tangxifan
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8e381f0581
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add wire module builder
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2020-02-12 19:57:15 -07:00 |
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tangxifan
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e842150cc5
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add lut module builder
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2020-02-12 19:52:41 -07:00 |
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tangxifan
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fddd3c9463
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add mux module builder
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2020-02-12 19:45:14 -07:00 |
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tangxifan
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ea7d879b4f
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add decoder module builder
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2020-02-12 18:28:50 -07:00 |
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tangxifan
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f11832b8cf
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |
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tangxifan
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13fadd0f91
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move compact routing hierarchy to build_fabric command
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2020-02-12 15:49:47 -07:00 |
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tangxifan
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df3ae60954
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add default configurable memory model set-up when reading openfpga architecture XML
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2020-02-12 15:19:40 -07:00 |
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tangxifan
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c78d3e9af1
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add mux library builder
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2020-02-12 14:58:23 -07:00 |
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tangxifan
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ce63b1cc62
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add circuit model binding for direct connections and enhance model type checking
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2020-02-12 11:40:20 -07:00 |
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tangxifan
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4a05cec037
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add rr_segment binding to circuit model
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2020-02-12 11:21:40 -07:00 |
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tangxifan
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a736e09c29
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add rr_switch binding in link openfpga arch command
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2020-02-12 10:52:20 -07:00 |
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tangxifan
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feccbc5780
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add more methods to link routing to circuit models in device annotation
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2020-02-12 10:08:54 -07:00 |
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tangxifan
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a31d6c6d1e
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rename pb_type annotation to device annotation
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2020-02-12 09:52:18 -07:00 |
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tangxifan
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4367dba9b7
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move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
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2020-02-11 21:02:58 -07:00 |
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tangxifan
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175bef014a
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add compact_routing hierarchy command
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2020-02-11 17:40:37 -07:00 |
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tangxifan
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1372f748f1
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put GSB builder online
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2020-02-11 16:37:14 -07:00 |
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tangxifan
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e2e115e6f3
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improve rr_node fast look-up in rr_graph object so that we have easily find all the channel nodes
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2020-02-11 11:33:30 -07:00 |
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tangxifan
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85f3826939
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put device rr_gsb online. Ready to plug-in
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2020-02-09 14:58:23 -07:00 |
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tangxifan
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230c7b709a
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put rr_gsb data structure online
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2020-02-09 00:20:44 -07:00 |
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tangxifan
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0b6b3bc029
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start adapting rr_gsb related data structure
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2020-02-07 11:32:33 -07:00 |
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tangxifan
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3d7eff64b9
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bug fixed for lut truth table fixup. Results look good
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2020-02-06 17:47:25 -07:00 |
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tangxifan
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ed9e038845
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add functionality of LUT truth table fix-up
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2020-02-06 17:14:29 -07:00 |
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tangxifan
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99f5a86b49
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bug fixed for routing annotation and routing net fix-up
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2020-02-06 12:54:55 -07:00 |
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tangxifan
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cccbb9fd49
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add missing files
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2020-02-05 22:12:44 -07:00 |
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tangxifan
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dad204674b
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done an initial version of clustering net fix-up based on routing results. Debugging on the way
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2020-02-05 21:50:52 -07:00 |
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tangxifan
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e89d8e4493
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bug fix for clock connection builder by supporting fake switch when adding edges to RRGraph object
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2020-02-04 21:56:54 -07:00 |
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tangxifan
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7092ddbde6
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bug fix for root node builder by including ptc_num!!
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2020-02-04 21:54:03 -07:00 |
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tangxifan
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e2f408cc2d
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bug fix for clock network builder using rr_graph object
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2020-02-04 21:32:05 -07:00 |
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tangxifan
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ecc3b8a4f0
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bug fix in router lookhead map when find rr_graph nodes
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2020-02-04 21:02:55 -07:00 |
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tangxifan
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a3a85bf259
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bug fix for direct connections in rr_graph builder
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2020-02-04 20:45:14 -07:00 |