Maciej Kurc
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66745a85f2
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Fixed an issue with the CI workflow
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2021-03-15 09:29:37 +01:00 |
Maciej Kurc
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02967f2870
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Added writing rr graph node indices to GSB dump.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2021-03-15 09:28:38 +01:00 |
tangxifan
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c8d41b4e69
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[Tool] Change routing module port naming to include architecture port names
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2021-03-14 19:35:49 -06:00 |
tangxifan
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956b9aca01
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[Tool] Trim dead codes in port naming function
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2021-03-13 20:23:08 -07:00 |
tangxifan
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2c5634ee76
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[Tool] Change pin naming of grid modules to be related to architecture port names
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2021-03-13 20:05:18 -07:00 |
tangxifan
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07257d0ff0
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[Tool] Patch wrong paths in FPGA-SDC
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2021-03-13 10:58:03 -07:00 |
tangxifan
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e61857aa2b
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Merge branch 'master' into ganesh_dev
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2021-03-11 19:17:02 -07:00 |
tangxifan
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74785f328c
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Merge pull request #263 from lnis-uofu/yosys_bump
update yosys submodule with ff and shift register mapping support for quicklogic architecture
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2021-03-11 19:16:40 -07:00 |
tangxifan
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366bec232c
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[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI
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2021-03-11 15:25:48 -07:00 |
tangxifan
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bb2a02c9ad
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[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v]
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2021-03-11 15:23:14 -07:00 |
tangxifan
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baf162e401
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[Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification
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2021-03-10 22:45:19 -07:00 |
tangxifan
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ff0faeb285
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[Doc] Update documentation about the extended bitstream setting
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2021-03-10 21:41:59 -07:00 |
tangxifan
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d877a02534
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[Tool] Patch the extended bitstream setting support on mode-select bits
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2021-03-10 21:28:09 -07:00 |
tangxifan
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85640a7403
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[Tool] Extend bitstream setting to support mode bits overload from eblif file
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2021-03-10 20:45:48 -07:00 |
tangxifan
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a6186db315
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[Test] Update bitstream annotation with new syntax
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2021-03-10 20:45:17 -07:00 |
tangxifan
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7d07f5d8cb
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[Test] Update bitstream setting example with mode bit overwriting
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2021-03-10 15:34:53 -07:00 |
tangxifan
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b42541d84e
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[Flow] Support multiple iterations in rewriting yosys scripts
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2021-03-10 14:10:35 -07:00 |
tangxifan
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90a00da1df
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[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'
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2021-03-10 13:56:35 -07:00 |
tangxifan
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d21909ad6c
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[Test] Use custom rewriting script in lut_adder test
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2021-03-10 13:48:20 -07:00 |
tangxifan
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0e772bc3b4
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[Script] Patch the yosys rewrite script to avoid existing blif outputs
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2021-03-10 13:47:30 -07:00 |
tangxifan
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7adb78b159
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[Script] Add a template yosys script with rewriting at the end
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2021-03-10 13:40:31 -07:00 |
tangxifan
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035043d0d8
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[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
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2021-03-10 13:36:11 -07:00 |
tangxifan
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5d46537b5b
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[Script] Allow users to specify custom post-synthesis verilog for simulation
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2021-03-10 11:45:55 -07:00 |
tangxifan
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aafd87c3f9
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[Flow] Update flow-run to support custom yosys rewrite scripts
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2021-03-10 11:36:29 -07:00 |
Tarachand Pagarani
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b138d36625
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update yosys module with async preset support
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2021-03-10 10:14:42 -08:00 |
Tarachand Pagarani
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db8ea86b2f
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update tests to use no_ff_map and remove tests that need async set/reset for now
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2021-03-10 10:04:45 -08:00 |
Tarachand Pagarani
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608bd1f658
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comment out desings that utilize local async reset/preset
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2021-03-09 19:24:01 -08:00 |
Tarachand Pagarani
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7f4c20ff33
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comment out desings that utilize local async reset/preset
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2021-03-09 10:37:06 -08:00 |
Tarachand Pagarani
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c4b83aeaa9
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bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type
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2021-03-09 00:46:40 -08:00 |
Tarachand Pagarani
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1c6606db5c
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Merge branch 'master' into yosys_bump
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2021-03-09 00:37:59 -08:00 |
tangxifan
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2daa770319
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[Arch] Update openfpga architecture to include quicklogic cell sim
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2021-03-08 21:40:29 -07:00 |
tangxifan
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812d8c950e
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[Script] Update quicklogic's script to output correct verilog file name
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2021-03-08 21:39:44 -07:00 |
tangxifan
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37aa42d305
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[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
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2021-03-08 21:38:51 -07:00 |
tangxifan
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c53c41b7a5
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[Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file
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2021-03-08 21:09:23 -07:00 |
tangxifan
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131643dcc0
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[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
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2021-03-08 21:08:55 -07:00 |
ganeshgore
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b860722893
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Fixed parameter ys_rewrite_params name bug
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2021-03-08 10:34:39 -07:00 |
ganeshgore
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52de55e7eb
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Merge branch 'master' into ganesh_dev
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2021-03-08 10:15:06 -07:00 |
tangxifan
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a1aade5d01
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Merge pull request #265 from lnis-uofu/shift_reg
add shift register test case
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2021-03-08 09:49:22 -07:00 |
tangxifan
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906d2fa72d
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Merge branch 'master' into shift_reg
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2021-03-08 09:24:29 -07:00 |
tangxifan
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f5a5f31a0e
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Merge pull request #262 from lnis-uofu/add_yosys_options
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically p…
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2021-03-08 09:23:24 -07:00 |
Ganesh Gore
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7a35811430
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[Flow] Yosys rewrite support
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2021-03-08 00:35:47 -07:00 |
Ganesh Gore
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67cd9a69b7
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[Flow] Extended yosys variable subtitution
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2021-03-08 00:21:07 -07:00 |
Lalit Sharma
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7945628307
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Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification
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2021-03-07 22:25:01 -08:00 |
Lalit Sharma
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6a1ce01084
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Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
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2021-03-07 22:02:11 -08:00 |
Tarachand Pagarani
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ce76c58422
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add shift register test case
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2021-03-05 09:06:05 -08:00 |
Lalit Sharma
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2b2acae757
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Adding command to generate verilog file out of yosys run
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2021-03-05 04:07:02 -08:00 |
Tarachand Pagarani
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d6464fa7cc
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update yosys submodule
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2021-03-04 03:16:21 -08:00 |
Lalit Sharma
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0cbad747a1
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Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
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2021-03-04 01:10:47 -08:00 |
Lalit Narain Sharma
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57a4bccbac
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Merge branch 'master' into add_yosys_options
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2021-03-03 10:25:59 +05:30 |
tangxifan
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e6d1ac4a58
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Merge pull request #260 from lnis-uofu/gg_ci_cd_dev
[CI/CD] Skipped container login if branch is not master
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2021-03-02 08:46:49 -07:00 |