AurelienUoU
|
0da9e50b20
|
Modify readme
|
2019-07-09 11:58:39 -06:00 |
Baudouin Chauviere
|
589f58b55e
|
Regression test succeeded
|
2019-07-09 09:18:06 -06:00 |
|
Baudouin Chauviere
|
25f5bc7792
|
Latest version, not stable yet but close
|
2019-07-09 08:34:01 -06:00 |
tangxifan
|
5d5e09fcdb
|
minor fix in trying to accelerate the unique routing functions
|
2019-07-08 17:12:36 -06:00 |
|
AurelienUoU
|
c3b34a6297
|
Update font in tutorial
|
2019-07-08 16:26:29 -06:00 |
|
AurelienUoU
|
8366f9e7b7
|
Update tutorial
|
2019-07-08 16:18:08 -06:00 |
|
AurelienUoU
|
f1ccf85bb9
|
Update tutorial -> fpga_flow explanation
|
2019-07-08 11:51:04 -06:00 |
|
AurelienUoU
|
9f16bb5998
|
Synthax correction 2 -> new line
|
2019-07-08 10:36:58 -06:00 |
|
AurelienUoU
|
c1ae3059c4
|
Correct synthax error
|
2019-07-08 10:32:39 -06:00 |
|
AurelienUoU
|
b2717abc3e
|
Replace obsolete example folder and start tutorial
|
2019-07-08 10:30:26 -06:00 |
|
Baudouin Chauviere
|
df0a3d23a3
|
Correction top module
|
2019-07-08 10:23:14 -06:00 |
|
Baudouin Chauviere
|
ae05c553d5
|
Top module done
|
2019-07-08 09:48:33 -06:00 |
|
tangxifan
|
fb064daded
|
Merge branch 'tileable_routing' into dev
|
2019-07-05 21:15:59 -06:00 |
|
tangxifan
|
76fefdb876
|
bug fixing in Fc_in and be serious in the performance of rr_graph
|
2019-07-05 16:23:15 -06:00 |
|
tangxifan
|
c62762ce59
|
bug fixing in assign ipins to tracks using Fc_in
|
2019-07-05 13:42:22 -06:00 |
|
AurelienUoU
|
df53f6da2c
|
Updates FPGA-Verilog command lines
|
2019-07-05 13:41:34 -06:00 |
|
tangxifan
|
64d8e9663a
|
minor fix to satisfy Fc_in and Fc_out
|
2019-07-05 13:13:35 -06:00 |
|
AurelienUoU
|
b4a78abc04
|
Update doc
Merge remote-tracking branch 'origin/heterogeneous' into dev
|
2019-07-05 12:25:37 -06:00 |
|
AurelienUoU
|
9e99048815
|
Update documentation
Merge branch 'heterogeneous' of https://github.com/LNIS-Projects/OpenFPGA into heterogeneous
|
2019-07-05 11:56:02 -06:00 |
|
AurelienUoU
|
27dbc527a0
|
Update Readme
|
2019-07-05 11:06:55 -06:00 |
|
AurelienUoU
|
f56adc6815
|
Update documentation
|
2019-07-05 10:20:16 -06:00 |
|
tangxifan
|
3077efa74f
|
add option to compact tileable routing arch
|
2019-07-04 17:13:34 -06:00 |
|
tangxifan
|
c8ceb8f7d5
|
update fpga_flow.pl
|
2019-07-04 12:23:11 -06:00 |
|
tangxifan
|
5a50fa84d1
|
keep updating fpga_flow.pl to use system call
|
2019-07-03 22:57:43 -06:00 |
|
tangxifan
|
d64aeef5c4
|
add profiling to routing compact process
|
2019-07-03 16:57:34 -06:00 |
|
tangxifan
|
1a1da30ae9
|
fixed a critical bug in using tileable route chan W
|
2019-07-03 16:46:43 -06:00 |
|
tangxifan
|
6b894640c7
|
bug fixing in fpga_flow.pl
|
2019-07-03 14:59:05 -06:00 |
|
tangxifan
|
b79d276ea9
|
add profiling to fpga_x2p_setup
|
2019-07-03 14:44:54 -06:00 |
|
tangxifan
|
d5137eb424
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
|
2019-07-03 14:31:18 -06:00 |
|
tangxifan
|
5195faab8b
|
Merge branch 'dev' into tileable_routing
|
2019-07-03 14:30:39 -06:00 |
|
tangxifan
|
4f3cb0bdf3
|
added tileable routing chanW adaption to fixed W router
|
2019-07-03 14:29:50 -06:00 |
Ganesh Gore
|
443a73954f
|
Removed all local files
+ Removed local configurations and scripts from previous commit
|
2019-07-03 14:26:06 -06:00 |
|
tangxifan
|
c9743e84da
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-03 14:12:47 -06:00 |
|
tangxifan
|
45b00e0881
|
Merge branch 'dev' into tileable_routing
|
2019-07-03 14:11:45 -06:00 |
|
tangxifan
|
a539c6a2a7
|
bug fixing in fpga_flow.pl
|
2019-07-03 14:11:14 -06:00 |
|
Ganesh Gore
|
57ad71438b
|
Merging ganesh_dev to dev
- Added spice_tool option in fpga_flow
- Some local customization
|
2019-07-03 13:39:52 -06:00 |
|
AurelienUoU
|
e13c703709
|
Upload recent commit
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-07-03 13:09:34 -06:00 |
|
AurelienUoU
|
43e9d8afd1
|
Add compact routing hierarchy option in fpga_flow
|
2019-07-03 13:08:49 -06:00 |
|
Ganesh Gore
|
3c36a51011
|
Added 'rewrite_path_in_file' back to repository
|
2019-07-03 12:49:25 -06:00 |
|
Ganesh Gore
|
53486b8a89
|
Added 'spice_simulator_path' in fpga_flow
added vpr_fpga_spice_simulator_path in fpga-flow script
|
2019-07-03 12:30:56 -06:00 |
|
tangxifan
|
570f9495e6
|
Merge branch 'tileable_routing' into dev
|
2019-07-03 12:13:48 -06:00 |
|
tangxifan
|
0c3e8bb70a
|
add a new option to the router to enable conversion of route_chan_width to be tileable
|
2019-07-03 12:11:48 -06:00 |
|
AurelienUoU
|
e0793c891a
|
Update demo
|
2019-07-03 12:04:55 -06:00 |
|
tangxifan
|
ea7e119313
|
Merge branch 'tileable_routing' into dev
|
2019-07-03 10:37:27 -06:00 |
|
tangxifan
|
02398818a9
|
update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area
|
2019-07-03 10:33:02 -06:00 |
|
tangxifan
|
547c479d84
|
Merge branch 'tileable_routing' into dev
|
2019-07-02 16:26:51 -06:00 |
|
tangxifan
|
4392c6bc3a
|
bug fixing in fpga_flow scripts and add more print-out message for VPR
|
2019-07-02 15:34:59 -06:00 |
|
Baudouin Chauviere
|
b08513d902
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
|
tangxifan
|
3e2a4917f5
|
Merge branch 'tileable_routing' into dev
|
2019-07-02 10:37:25 -06:00 |
|
AurelienUoU
|
60f7ab0465
|
Start heterogeneous dev
|
2019-07-02 10:16:10 -06:00 |