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Synthax correction 2 -> new line

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AurelienUoU 2019-07-08 10:36:58 -06:00
parent c1ae3059c4
commit 9f16bb5998
1 changed files with 30 additions and 28 deletions
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tutorials/tutorial.md
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@ -27,7 +27,7 @@ fpga_flow.pl has dependencies which need to be configured. They are:
### Configuration file
In this file paths have to be full path. Relative path could lead to errors.
In this file paths have to be full path. Relative path could lead to errors.<br />
The file is organized in 3 parts:
- dir_path: provides all the tools and repository path
- flow_conf: provides information on how the flow run
@ -35,32 +35,34 @@ The file is organized in 3 parts:
While empty the file is as follow:
[dir_path]
script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts
benchmark_dir = *Path to the folder containing all sources of the design*
yosys_path = OPENFPGAPATHKEYWORD/yosys
odin2_path = not_used
cirkit_path = not_used
abc_path = OPENFPGAPATHKEYWORD/abc
abc_mccl_path = OPENFPGAPATHKEYWORD/abc
abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc
mpack1_path = not_used
m2net_path = not_used
mpack2_path = not_used
vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr
rpt_dir = *wherever tou want logs to be saved*
ace_path = OPENFPGAPATHKEYWORD/ace2
[dir_path]<br />
script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts<br />
benchmark_dir = *Path to the folder containing all sources of the design*<br />
yosys_path = OPENFPGAPATHKEYWORD/yosys<br />
odin2_path = not_used<br />
cirkit_path = not_used<br />
abc_path = OPENFPGAPATHKEYWORD/abc<br />
abc_mccl_path = OPENFPGAPATHKEYWORD/abc<br />
abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc<br />
mpack1_path = not_used<br />
m2net_path = not_used<br />
mpack2_path = not_used<br />
vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr<br />
rpt_dir = *wherever tou want logs to be saved*<br />
ace_path = OPENFPGAPATHKEYWORD/ace2<br />
[flow_conf]<br />
flow_type = yosys_vpr *to use verilog input*<br />
vpr_arch = *wherever the architecture file is saved*<br />
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK<br />
m2net_conf = not_used<br />
mpack2_arch = not_used<br />
power_tech_xml = *wherever the xml tech file is saved*<br />
[csv_tags] *to complete*<br />
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:<br />
mpack2_tags = BLE Number:|BLE Fill Rate: <br />
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:<br />
vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff<br />
[flow_conf]
flow_type = yosys_vpr *to use verilog input*
vpr_arch = *wherever the architecture file is saved*
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = not_used
mpack2_arch = not_used
power_tech_xml = *wherever the xml tech file is saved*
[csv_tags] *to complete*
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
mpack2_tags = BLE Number:|BLE Fill Rate:
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff