tangxifan
|
33a253da3d
|
[core] fixed the bug
|
2024-09-20 22:20:41 -07:00 |
|
tangxifan
|
6551ca81e5
|
[core] debugging
|
2024-09-20 19:48:02 -07:00 |
|
tangxifan
|
6d3d36626e
|
[test] typo
|
2024-09-20 19:29:47 -07:00 |
|
tangxifan
|
ed33b62a60
|
[test] add new tests to validate intermediate drivers in clock
|
2024-09-20 19:27:40 -07:00 |
|
tangxifan
|
7b4f06ed7d
|
[test] validate mux2 at last stage
|
2024-09-18 17:40:13 -07:00 |
Jingrong Lin
|
77b188060b
|
Merge branch 'master' into preloading_clean
|
2024-09-11 11:08:49 +08:00 |
victorzh001
|
04a60ca4b5
|
Merge branch 'master' into victor_OpenFPGA_dbg
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2024-09-10 11:01:47 +08:00 |
|
tangxifan
|
f912af513b
|
[test] add a new testcase to validate mapping gnet to msb during pb_pin_fix
|
2024-09-09 13:54:20 -07:00 |
Victor
|
8d97ebd980
|
Add more test cases and update documentation about the YAML file format of this command
|
2024-09-09 17:49:10 +08:00 |
Lin
|
d15025d9d2
|
add a task case to ease the use of compress_routing option
|
2024-09-09 14:18:47 +08:00 |
|
Victor
|
83fc1210b5
|
add test case of report_reference to basic_reg_test.sh
|
2024-09-06 18:28:23 +08:00 |
|
Victor
|
9a2fc86dcd
|
add dependency on build_fabric
|
2024-09-06 17:58:47 +08:00 |
|
Victor
|
7bacc781d0
|
update code according to code review comments
|
2024-09-06 15:39:08 +08:00 |
|
Lin
|
1d35a17a8b
|
delete redundant file
|
2024-08-30 14:18:59 +08:00 |
|
Lin
|
acce64058c
|
add test case
|
2024-08-30 14:17:42 +08:00 |
|
Lin
|
8372eead6a
|
add preload flag to device_rr_gsb and revert change to build fabric
|
2024-08-28 18:14:33 +08:00 |
|
Lin
|
5153cee4dd
|
mod reg_test script
|
2024-08-26 02:47:13 -07:00 |
|
Lin
|
701a7a5c52
|
add test case
|
2024-08-26 02:45:57 -07:00 |
|
Lin
|
88fa9f8d39
|
add test case
|
2024-08-25 23:41:19 -07:00 |
|
tangxifan
|
05ef972911
|
[test] typo
|
2024-08-15 15:36:08 -07:00 |
|
tangxifan
|
2c35840457
|
[test] add a new test to validate CHANY clock spin in DEC
|
2024-08-15 14:24:31 -07:00 |
|
tangxifan
|
586dd1a510
|
[test] add a new and strong test to validate the disable unused clock spines
|
2024-08-15 10:24:58 -07:00 |
|
tangxifan
|
84cc7090ce
|
[test] add a new test to validate that pb pin fixup impacts global net now
|
2024-08-14 10:37:46 -07:00 |
|
tangxifan
|
542571ce89
|
[test] code format
|
2024-08-09 18:20:27 -07:00 |
|
tangxifan
|
c6246ae905
|
[test] typo
|
2024-08-09 17:10:51 -07:00 |
|
tangxifan
|
a05bfb55dd
|
[test] typo
|
2024-08-09 17:05:48 -07:00 |
|
tangxifan
|
38f1bdba4e
|
[test] add a new test case
|
2024-08-09 17:04:10 -07:00 |
|
tangxifan
|
602ab72002
|
[test] add associated openfpga arch
|
2024-08-09 17:01:23 -07:00 |
|
tangxifan
|
e6c508f081
|
[test] add a new arch to validate that clock network tap supports subtiles
|
2024-08-09 16:51:34 -07:00 |
|
tangxifan
|
1026df4890
|
[test] add new tests to validate the options for undriven inputs in verilog netlists
|
2024-08-06 20:58:00 -07:00 |
|
tangxifan
|
57adf97fd4
|
[test] fixed some bugs in clock arch
|
2024-08-02 18:34:59 -07:00 |
|
tangxifan
|
91c4336a4a
|
[test] add a new testcase to validate 3-layer clock architecture
|
2024-08-02 18:18:49 -07:00 |
|
tangxifan
|
84c2b27c7b
|
[test] add a new test to validate that pb_pin fix is now compatible with perimeter cb
|
2024-08-02 17:24:44 -07:00 |
chungshien
|
b3c8c529d5
|
Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits
|
2024-07-31 12:25:37 -07:00 |
|
tangxifan
|
3181f2d5a3
|
[test] add a new test to validate multiple entry points for a clock network
|
2024-07-30 14:17:14 -07:00 |
|
tangxifan
|
687f03fd77
|
[test] add a new test to validate clock network on module named by index
|
2024-07-30 14:06:53 -07:00 |
|
tangxifan
|
f9f9aab7d9
|
[test] typo
|
2024-07-30 12:50:14 -07:00 |
|
tangxifan
|
ad275fba44
|
[test] add a new test to validate clock network entry point on a y-direction cb
|
2024-07-30 12:48:35 -07:00 |
|
tangxifan
|
b6b038a73d
|
[test] add a new arch to test y- entry point of clock network
|
2024-07-30 12:40:41 -07:00 |
chungshien-chai
|
ca48841ae3
|
Pass in the OpenFPGA root dir
|
2024-07-29 11:04:03 -07:00 |
|
chungshien-chai
|
3e3f089823
|
Get the filepath using definition under [OpenFPGA_SHELL]
|
2024-07-28 19:24:48 -07:00 |
|
chungshien-chai
|
0d9f1a3c6b
|
Forward searching the config bit + some minor refactor
|
2024-07-28 19:12:34 -07:00 |
|
chungshien-chai
|
933155b08f
|
Update test flow
|
2024-07-27 23:52:54 -07:00 |
|
chungshien-chai
|
fbe5ae6bd3
|
Update test
|
2024-07-26 02:18:08 -07:00 |
|
chungshien-chai
|
9641aaf6c4
|
Update test
|
2024-07-26 02:17:25 -07:00 |
|
chungshien-chai
|
2ef362d53d
|
Init support overwriting bitstream
|
2024-07-25 17:40:46 -07:00 |
|
tangxifan
|
e614ca7380
|
[test] use new syntax
|
2024-07-10 15:03:27 -07:00 |
|
tangxifan
|
977283dd34
|
[core] typo
|
2024-07-10 14:12:49 -07:00 |
|
tangxifan
|
af996e563e
|
[test] add a new test to validate reset generated by internal driver through programmable clock network
|
2024-07-10 14:11:06 -07:00 |
|
tangxifan
|
b6ff69faac
|
[test] reworking the testcase to validate clock network with internal drivers
|
2024-07-10 11:36:22 -07:00 |