tangxifan
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b8187bbca5
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fix a bug for supporting default circuit_model of LUTs and FFs
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2019-01-10 15:10:05 -07:00 |
Baudouin Chauviere
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9c8444da43
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update of the examples supplied to get the right paths
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2019-01-10 00:06:20 -07:00 |
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Baudouin Chauviere
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4ae3aa517c
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go.sh replaces the paths now
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2019-01-09 23:16:43 -07:00 |
|
Baudouin Chauviere
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510c27f816
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Removed commercial scripts, replaced by academia ones
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2019-01-09 11:56:07 -07:00 |
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Baudouin Chauviere
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3b4fc16c60
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Adding help message on the go.sh
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2019-01-09 11:54:28 -07:00 |
|
tangxifan
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66701838ff
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update relative path in ARCH XML
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2019-01-08 11:41:24 -07:00 |
AurelienUoU
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b80e435548
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Correct manual testbench generation bug
|
2019-01-07 18:03:56 -07:00 |
BaudouinChauviere
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5dbcfa6d70
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Repair broken link
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2019-01-03 18:26:30 +01:00 |
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BaudouinChauviere
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28010f6c91
|
Testing another link method
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2019-01-03 18:24:06 +01:00 |
Laboratory for Nano Integrated Systems (LNIS)
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30f2ada557
|
Repaired broken links
|
2019-01-03 18:18:03 +01:00 |
|
tangxifan
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349e634fef
|
Update README.md
|
2018-12-30 14:37:17 -07:00 |
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tangxifan
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9f3da4d1a5
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Update README.md
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2018-12-30 14:35:07 -07:00 |
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LNIS-Projects
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77dd7f3e04
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correction of the name of the figure
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2018-12-29 01:45:45 +01:00 |
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LNIS-Projects
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0f6ac32f43
|
Further resizing
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2018-12-29 01:44:24 +01:00 |
|
LNIS-Projects
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38a3b01520
|
Resize the images
|
2018-12-29 01:42:43 +01:00 |
|
Baudouin Chauviere
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9ee50de26a
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Adding information on the layout
|
2018-12-29 01:14:26 +01:00 |
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Baudouin Chauviere
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0a5391c14f
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Addition of some illustrations
|
2018-12-26 18:16:16 +01:00 |
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LNIS-Projects
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de7d646fa0
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Update func_verify.rst
Functional Verification documentation
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2018-12-26 18:05:24 +01:00 |
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LNIS-Projects
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c0626e9a1c
|
Adding the Verification Step from ModelSim
|
2018-12-26 18:00:03 +01:00 |
|
AurelienUoU
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7ff245448b
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Add new benchmark and modify go.sh to use it
|
2018-12-26 04:24:26 -07:00 |
|
LNIS-Projects
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c506e16d33
|
Update command_line_usage.rst
Small fix
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2018-12-22 14:46:15 +01:00 |
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LNIS-Projects
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ba303450e2
|
Update file_organization.rst
|
2018-12-22 14:45:00 +01:00 |
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LNIS-Projects
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5fa6c84087
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New fpga_verilog commands documented
|
2018-12-22 14:39:51 +01:00 |
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LNIS-Projects
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41067f6ac1
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Update .travis.yml
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2018-12-14 16:13:05 -07:00 |
Robert Weischedel
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1b6d5b3b5d
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Update .travis.yml
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2018-12-14 15:30:25 -07:00 |
|
AurelienUoU
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2fd05f269e
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
|
2018-12-14 14:49:04 -07:00 |
|
AurelienUoU
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21dc8a006f
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Change simulator script generation (waves)
|
2018-12-14 14:40:04 -07:00 |
|
LNIS-Projects
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c0e49b7d4d
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Update .travis.yml
|
2018-12-14 14:16:04 -07:00 |
|
LNIS-Projects
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c7915511f7
|
Update .travis.yml
|
2018-12-14 14:12:26 -07:00 |
|
LNIS-Projects
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74c1067220
|
Update .travis.yml
|
2018-12-14 14:09:09 -07:00 |
|
tangxifan
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1d426986e5
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add travis
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2018-12-14 14:05:31 -07:00 |
|
tangxifan
|
ee6b1d6cd6
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adapt arch xml and act for demo
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2018-12-13 22:46:40 -07:00 |
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tangxifan
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3d9e913e4e
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add a benchmark fifo
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2018-12-12 16:45:33 -07:00 |
|
AurelienUoU
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cc5a01d476
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Fix waveform generation + add benchmark and update go.sh
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2018-12-11 22:21:39 -07:00 |
|
AurelienUoU
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a70b0ac9ac
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Correct go.sh
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2018-12-11 15:51:21 -07:00 |
|
AurelienUoU
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317c3b59c9
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Update go.sh and upload pip_add.v
|
2018-12-11 15:47:05 -07:00 |
|
AurelienUoU
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fb0992bd85
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Update go.sh and Makefile
|
2018-12-11 15:31:32 -07:00 |
|
AurelienUoU
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c2c4e78639
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Add pip_add benchmark
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2018-12-11 15:29:48 -07:00 |
|
AurelienUoU
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f5ea3ff233
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Add an autochecked configuration free testbench
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2018-12-11 14:44:13 -07:00 |
|
Baudouin Chauviere
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79f3db9880
|
removed the now useless tutorial part
|
2018-12-10 13:57:01 -07:00 |
|
Baudouin Chauviere
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ba6ace343b
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
|
2018-12-10 13:48:09 -07:00 |
|
LNIS-Projects
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55459f7906
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Update index.rst
Reorganization
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2018-12-10 13:46:38 -07:00 |
|
LNIS-Projects
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56555fc8a0
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Update index.rst
Removed abc from the project because included in Yosys
|
2018-12-10 13:46:02 -07:00 |
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tangxifan
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8891904e10
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
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2018-12-10 13:30:12 -07:00 |
|
tangxifan
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72fbd8d6a8
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update blif reader to identify clock signals
|
2018-12-10 13:28:44 -07:00 |
|
LNIS-Projects
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7bcc61b0f2
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Update .gitmodules
Unused submodule blocking the compilation of the documentation
|
2018-12-10 12:07:05 -07:00 |
|
Baudouin Chauviere
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1472e7aa62
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
|
2018-12-10 10:25:25 -07:00 |
|
AurelienUoU
|
a69c2e1882
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Add security in checking to avoid simulation glitch error
|
2018-12-10 09:46:16 -07:00 |
|
AurelienUoU
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7020d9b4b6
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Edit waveform generator + fix clock mapping in autochecked testbench
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2018-12-09 15:48:59 -07:00 |
|
Baudouin Chauviere
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afbe5bd3ff
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need abc_with_bb_support for ace compilation
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2018-12-09 15:45:09 -07:00 |