The "Blue Pill" is a popular development board with an STM32F103C8
micro controller. According to sources, it has a 128kB Flash on board
even though the option bytes only report 64kB. This patch therefore also
modifies target/stm32f1x.cfg to take an optional FLASH_SIZE variable into
account which the board file sets to 0x20000.
Change-Id: I8a78ccd2b5faf637c539ee3cf8136789ee15c95d
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4495
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add configuration for the Renesas R-Car R8A7790 H2 target.
This is an SoC with four Cortex A15 and four Cortex A7
ARMv7a cores, only the four A15 cores are supported.
Change-Id: I6099b257cc0f04e6858ed5f5f8c8d8ad82ef7650
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/4490
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The Vybrid VF6xx SoCs contain an additional Cortex-M4
core connected to AP number 3 of the main DAP.
Change-Id: I59c020fdfc53e909b1f0dac1a8627a62cdaa74f2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3640
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
includes target configuration for i.MX8M SoC family,
board file needs to set up CHIPNAME and CHIPCORES
to match the actual hardware configuration
Change-Id: Ieb6d89cab2477a58f85d0ef9cd242710950191c0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4434
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
configuration also contains a reset-init procedure that disables the
watchdog and initilizes the boards DDR memory so that you can upload
baremetal (e.g. boot loader) code into DDR and start it from there.
Change-Id: I4d2311b3708a5fcb5174a3447f34ae3904de7243
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4227
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Add configuration for the Renesas R-Car R8A7791 M2W target.
This is an SoC with two Cortex A15 ARMv7a cores, both cores
are supported.
This patch is based on initial submission by Adam Bass and
improvements by Niklas Söderlund.
Change-Id: I297da62b9ce71ad222a401d98e6bcb8502427673
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Adam Bass <adam.bass@renesas.com>
Cc: Niklas Söderlund <niklas.soderlund@ragnatech.se>
Reviewed-on: http://openocd.zylin.com/4485
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Most Xilinx FPGA devices contain an embedded, unique device identifier.
The identifier is nonvolatile, permanently programmed into the FPGA, and is
unchangeable providing a great serial / tracking number.
This commit adds generic support for reading the Xilinx Spartan 6 and 7
Series (Kintex, Artix, Ultrascale) Device DNA. The code is similar to
the function in fpga/xilinx-xc6s.cfg for Spartan 6 but the register
addresses are different and the logic has been simplified.
The code was not placed in xilinx-xc7.cfg. The approach of defining taps
in the same file as library code to use them is fundamentally broken on
boards that have more than one FPGA or other chips. This commit (like
the addition of support for Xilinx XADC) starts to remedy that by
splitting library code from board-specific fixed definitions.
The support code is sourced in the Kasli and KC705 board support files
as it was tested on these boards.
Change-Id: Iba559c7c1b7e93e1270535fd9e6650007f3794da
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4396
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
temperature, internal power supply rail voltages as well as external
voltages. The XADC is available both from fabric as well as through the
JTAG TAP.
This code implements access throught the JTAG TAP.
https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
Change-Id: I6cef4d0244add71749fa28b58a736302151cc4dd
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4395
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Kasli is an open hardware FPGA board. It is part of the Sinara family of
devices designed to control quantum physics experiments (see Sayma_AMC
for other boards already suppported by openocd).
Kasli was developed as part of the opticlock project. It features a
Xilinx Artix 7 100T FPGA, DDR3 RAM, a clock reconstruction and
distribution network, four 6 Gb/s transceiver links (three SFP and
one SATA) as well as interfaces to up to 12 Eurocard Extension Modules
(EEMs).
https://github.com/m-labs/sinara/wiki/Kaslihttp://www.opticlock.de/en/
Change-Id: I88b5e9f16b79e1e731056c45da6b5e1448d2c0e7
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4341
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The Ultrascale series is a bit more complicated to handle since with the
stacked and interconnected dies the IR gets longer. This adds support
for all currently known chips from the Ultrascale family.
Change-Id: Ibac325dd6fadc76f73cc682b1c62c1a5f39f0786
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4188
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
- add 'dap create' command to create dap instances
- move all dap subcmmand into the dap instance commands
- keep 'dap info' for convenience
- change all armv7 and armv8 targets to take a dap
instance instead of a jtag chain position
- restructure tap/dap/target relations, jtag tap no
longer references the dap, daps are now independently
created and initialized.
- clean up swd connect
- re-initialize DAP also on JTAG errors (e.g. after reset,
power cycle)
- update documentation
- update target files
Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4468
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Extend the CTI abstraction to be accessible from TCL and
change the 'target' command to accept a cti 'object' instead of a
base address. This also allows accessing CTI instances that are not
related to a configured target.
Change-Id: Iac9ed0edca6f1be00fe93783a35c26077f6bc80a
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4031
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Make sure the user is aware he can lock the device though unlock is not
possible without access to MDM-AP.
Change-Id: I92676530e95d19489c6739748a99c2895849f90f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4403
Tested-by: jenkins
When a user asks for blaster I, he or she should either get it, or get
an error, not blaster II driver.
Change-Id: Ibc7683676ce42773e2b14ea5ccb3d119d1e6acea
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4381
Tested-by: jenkins
This is a second try for this patch. I removed the queues from the
previous version. I made it compatible with SRST reset and added
support for those features that could be supported in raw binary
mode.
Change-Id: I96fc06abbea9873e98b414f34afd9043fd9c2a41
Signed-off-by: Mateusz Manowiecki <segmentation@fault.pl>
Reviewed-on: http://openocd.zylin.com/3960
Tested-by: jenkins
Reviewed-by: Eric Work <work.eric@gmail.com>
Reviewed-by: Thomas Jarosch <thomas.jarosch@intra2net.com>
Reviewed-by: Jacob Alexander <haata@kiibohd.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
30 MHz is not working reliably here
Change-Id: I38f5f8c7153fc64e313ee911b1629fb5f1114c39
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4242
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This makes it possible to program newer EFM32 and EFR32 chips with
JTAG, as opposed to SWD.
Change-Id: Ia3e8c1bbc66fc1f33e8cf2087ccf0d1b4dfd74e1
Signed-off-by: Jonas Norling <jonas.norling@cyanconnode.com>
Reviewed-on: http://openocd.zylin.com/4262
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The ICEPick-D jtag router has core control registers
that provide the same (or similar) functionality as
the tap control register, for individual cores
accessible through the same tap (e.g. through a DAP).
Core control registers are located at address "0x60 +
core-id" of the ROUTER address space (IR=ROUTER).
It is sometimes helpful or even necessary to modify the
core control register. This patch renames the
"icepick_d_coreid" function to the more appropriate
"icepick_d_core_control" and adds a "value" argument
that allows writing of arbitrary value.
"icepick_d_tapenable" is extended by an optional value
argument so that core control can be written as the tap
is enabled.
Change-Id: I0e7f91b596cb5075364c6c233348508f58e0a901
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4141
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Flash ROM API command PSOC4_CMD_SET_IMO48 is now optional on new devices.
Also code tidy up:
- improved system ROM call error detection
- probe does not require the target to be halted
- default_padded_value and erased_value set to 0
- fixed endianess problem in flash write and protection setting
- removed fancy chip detection table as it would be updated too often
- psoc4 flash_autoerase is now on by default to ease programming
psoc4.cfg distinguishes chip family and uses either proprietary acquire
function of a KitProg adapter or TEST_MODE workaround to "reset halt"
Change-Id: I2c75ec46ed0a95e09274fad70b62d6eed7b9ecdf
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3807
Tested-by: jenkins
Reviewed-by: David Girault <david.f.girault@gmail.com>
Make all configs specify same JTAG and SWD GPIO numbers.
Change-Id: I65b09c1671c97f253f0aab88e511de7409d91e0a
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3932
Tested-by: jenkins
Some parts have only that much. Reported by robertfoos_ on IRC.
Change-Id: I684fdccfa62cf726466ddc467543a990fd88c4dc
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4369
Reviewed-by: Robert Foss <robert.foss@memcpy.io>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit contains a rewrite of the jtagspi protocol and covers both
changes in the jtagspi.c openocd driver and the bscan_spi
(xilinx_bscan_spi) proxy bitstreams. The changes are as follows:
1. Always perform IR scan to ensure proper clearing of BYPASSed DRs.
2. Insert alignment cycles for all BYPASSed TAPs:
The previous logic was erroneous. The delay in clock cyles from a bit
written to the jtag interface to a bit read by the jtag interface is:
* The number of BYPASSed TAPs before this (jtagspi) tap
* The length of the jtagspi data register (1)
* The number of BYPASSed TAPs before this one.
I.e. it is just the number of enabled TAPs. This also gets rid of the
configuration parameter DR_LENGTH.
3. Use marker bit to start spi transfer
If there are TAPs ahead of this one on the JTAG chain, and we are in
DR-SHIFT, there will be old bits toggled through first before the first
valid bit destined for the flash.
This delays the begin of the JTAGSPI transaction until the first high bit.
4. New jtagspi protocol
A JTAGSPI transfer now consists of:
* an arbitrary number of 0 bits (from BYPASS registers in front of the
JTAG2SPI DR)
* a marker bit (1) indicating the start of the JTAG2SPI transaction
* 32 bits (big endian) describing the length of the SPI transaction
* a number of SPI clock cycles (corresponding to 3.) with CS_N asserted
* an arbitrary number of cycles (to shift MISO/TDO data through
subsequent BYPASS registers)
5. xilinx_bscan_spi: clean up, add ultrascale
This is tested on the following configurations:
* KC705: XC7K325T
* Sayma AMC: XCKU040
* Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG
adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx
Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma
* Custom board with Lattice FPGA + XC7A35T
* CUstom board with 3x XCKU115-2FLVA1517E
Change-Id: I7361e9fb284ebb916302941735eebef3612aa103
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4236
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
* Disables the data output pin while SWD is reading, so that a simple FTDI
SWD interface can be made by connecting TCK to SWD_CLK and TDI+TDO directly
to SWDIO. Enabled by setting SWDIO_OE to 0.
Change-Id: I7d3b71cf3f4eea163cb320aff69ed95d219190bd
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Signed-off-by: Roger Lendenmann <roger.lendenmann@intel.com>
Reviewed-on: http://openocd.zylin.com/2274
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
The Digilent SMT2 NC is nominally the connector-less version of the
SMT2. But neither the SMT2 configuration nor the HS3 configuration work
for on the Xilinx KCU105 board where the SMT2 NC is used.
Change-Id: Ieb27cbc6d8b0f9c64ef778e4e0c839acc85ec0ef
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4187
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
We can now use the generic stlink.cfg which allows for both ST-LINK/V2
and V2-1 debuggers.
Change-Id: I229c6fe5f6a6a4f2d3c787a49939846f102f9e24
Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
Reviewed-on: http://openocd.zylin.com/4313
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Extend HLA interface to allow multiple VID/PID pairs and use it to
autodetect the connected stlink version.
Change-Id: I35cd895b2260e23cf0e8fcb1fc11a78c2b99c69b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3961
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
New low-end chips have only 2k of RAM, workarea size adjusted
Change-Id: Ibfccd73fef9e6dabffc87d901736c5626ce411fe
Signed-off-by: Ilia Motornyi <elijah.mot@gmail.com>
Reviewed-on: http://openocd.zylin.com/4308
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
New STM8 target based mostly on mips4k. Target communication
through STLINK/SWIM. No flash driver yet but it is still possible
to program flash through load_image command. The usual target debug
methods are implemented.
Change-Id: I7216f231d3ac7c70cae20f1cd8463c2ed864a329
Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com>
Reviewed-on: http://openocd.zylin.com/3953
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Similar to the Sheevaplug fix inf95f8b70fbd0f7e9c91a2d9006b1abb2dd07ebf2
the OpenRD device has its JTAG interface on the first channel of the
ft2232, which is 0 for the new driver but was 1 for the old one. Correct
the config file appropriately. Also the device description was missing
the trailing " B" and thus not picking up the device correctly. Finally
add an adapter_khz setting in the OpenRD board configuration file - set
to 2MHz to match the Sheeva variant.
Confirmed as working thanks to Phil Hands providing me access to his
hardware to test on.
See also Debian Bug#793214; https://bugs.debian.org/793214
Change-Id: Ifacf53124eaa330bbbdf36dfa79e3256bf2a5201
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4254
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This config covers the 4x Cortex A53 CPUs. A custom connector
is required from J14 to standard ARM JTAG on v1 boards. However
v2 hardware should have a standard FTSH-105-01-L-DV connector.
Pinmuxing code to enable JTAG pins is included in l-loader-poplar
repository, so board is flashed with open source code, JTAG
is available at very early boot. Alternatively the following
pokes can be issued from U-Boot to enable JTAG (e.g. to debug
hisilicon SDK).
mw 0xf8a210ec 0x130;
mw 0xf8a210f0 0x130;
mw 0xf8a210f4 0x130;
mw 0xf8a210f8 0x130;
mw 0xf8a210fc 0x130;
mw 0xf8a21100 0x130;
Change-Id: I2b83dfcb3dc5461c1620f94dd99aa7b31fdda59b
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-on: http://openocd.zylin.com/4161
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
in some cases we need something to test if uart is actually
properly connected.
Change-Id: I5a16b053164b34bb30ae8370753be12887a85c51
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4194
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Finally we can use this driver by default!
Change-Id: I09d215d1bd1dc16873a7379637e6869af65ad8f1
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4193
Tested-by: jenkins
Reviewed-by: Dmytro <dioptimizer@hotmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
- Tested on a real FT2232H MiniModule, so warning removed.
- Every pin initially set to high impedance except TCK, TDI,
TDO and TMS: Safest values given it's an evaluation board
and the rest of pins might be connected to something else.
- Reset is now initially de-asserted (it was asserted
which is not recommended).
- nRST pin choice is arbitrary so comment added (wondering
if it should be an "echo").
- "-oe" option added to NRST signal so it can be set as
high impedance (tri-stated).
Change-Id: I967ab0c7bbccf72dbf6d6d78b3180b74e016e0d6
Signed-off-by: Diego Herranz <diegoherranz@diegoherranz.com>
Reviewed-on: http://openocd.zylin.com/4185
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The migration from the old ft2232 driver to the new generic ftdi driver
ended up breaking support for the SheevaPlug device. The old driver
defaulted to channel 1, but numbered the channels 1 to 4. The new driver
starts at 0. The SheevaPlug JTAG is on interface A (interface B is the
serial console), so it should be using channel 0. Fix this. Confirmed
as working; serial console remains available and a new u-boot image can
be transferred across using the JTAG link.
See also Debian Bug#837989; https://bugs.debian.org/837989
Change-Id: I4ac2bfeb0d1e7e99d70fa47dc55f186e6af2c542
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4206
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
As found on the NI Project Sulfur SDR board.
Change-Id: I47bdd38ae85cf45cedad8797ea03bf3105153320
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: http://openocd.zylin.com/4176
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Active watchdog forces reset during armv7m_checksum_memory()
in verify_image command if run just after reset init.
COP watchdog in KL series and WDOG32 in KE1 series
have longer timeout however they need to be disabled too.
The change extends 'kinetis disable_wdog' command to optionally
probe the chip and use appropriate algorithm to disable watchdog.
Setting of cache type is also split from flash_support flags.
Tcl command 'kinetis disable_wdog' is called in reset-init event.
Change-Id: I3191e230f38b679ed74f2a97fe323ef8fb3fe22e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3901
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Kinetis flash driver services huge number of MCU types. They have
one, two or four flash banks with option of FlexNVM. It would
require ~36 config files just for Kx series, more for KLx, KVx and KE1x.
The change implements alternative approach:
- configuration file creates just one pflash bank (common for all devices)
- when a device is probed, additional pflash or flexnvm banks are created
based on flash layout of the connected MCU
- created banks have names with optional numbering e.g. kx.pflash0 kx.pflash1
kx.flexnvm0 kx.flexnvm1
- the first bank gets renamed if numbering is used
Automatic bank creation is enabled by tcl command 'kinetis create_banks'.
Used solution has a drawback: other banks than pflash0 are not accessible
until pflash0 is probed. Fortunately gdb attach and standard programming
accesses banks in right sequence.
Change-Id: I5b9037cbefdb8a4176b7715fbcc3af4da4c1ab60
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3925
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Config file renamed to ke0x.cfg and a notice added to texi.
While on ke0x.cfg CPUTAPID setting fixed: device has SWD port only, no JTAG.
Removed per device configs as they set CHIPNAME and nothing more.
Let's use reasonably universal chip name 'ke' set in family config.
Change-Id: I313db87a59f25f968eb3c27df155780b67becee8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3897
Tested-by: jenkins
Reviewed-by: Ivan Meleca <ivan@artekit.eu>
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The new Kinetis KE1x families use FTFE flash controller unlike KE0x.
Also SDID coding corresponds to new K, KL and KV families.
That's why KE1x is handled by kinetis driver instead of kinetis_ke
Change-Id: Ibb73e28e41dfbb086e761e1f006b089825dab854
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3896
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
For some targets (like nrf51) sysfs driver is too slow. This
patch implements memory maped driver for IMX processors.
Mostly based on bcm2835gpio. Tested on imx6ul CPU. However, it should
work on any NXP IMX CPU.
Change-Id: Idace4c98181c6e9c64dd158bfa52631204b5c4a7
Signed-off-by: Grzegorz Kostka <kostka.grzegorz@gmail.com>
Reviewed-on: http://openocd.zylin.com/4106
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This patch adds a driver for the SWD-only Cypress KitProg
programmer/debugger.
Change-Id: I3a9a8011a762781d560ebb305597e782a4f9a8e5
Signed-off-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-on: http://openocd.zylin.com/3221
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This patch adds the file ti_beaglebone-base.cfg as the common base
configuration for all TI BeagleBone derived boards. It also modifies
ti_beaglebone.cfg to source the base board and only add the on-board
JTAG adapter. Lastly, it adds a file ti_beaglebone_black.cfg with
a suitable configuraton for the BeagleBone "Black" variant.
Change-Id: I40cacb8abed7bdb308929713891f7b5e5b685c95
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3099
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
configuration covers all 8 Cortex-A53 cores and auxiliary Cortex-M3
used for power management.
Change-Id: I5509f275aa669abe285f9152935ecdcbcd0c402e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4009
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested with a Dresden Elektronik deRFmega128 module.
Change-Id: I91da3b11b60e78755360b08453ed368d6d396651
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/2790
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Commit 25d7ba19c9 introduced a problem
with 'reset halt' due to setting srst_pulls_trst:
Error: cortex_m.c:595 cortex_m_halt(): can't request a halt while
in reset if nSRST pulls nTRST
Sorry, I don't know why I overlooked it when I tested #3722.
Change-Id: I41e9473dd91a86d93cf3e78b1fbbdfe1dd188d83
Reported-by: Ladislav Laska <laska@kam.mff.cuni.cz>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3942
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This seems to be a leftover from borrowing from omap3* configs. Since
SJC is not enabling or disabling the DAP tap, and the tap is always
available, the extra tapenable command causes warnings on startup
(can't enable what's already enabled).
Change-Id: I7514436d565aa5b91876dbdab547956f36dcab77
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3892
Tested-by: jenkins
This patch contains configuration for the twr-vf65gs10 system module
of the Freescale (NXP) tower system. It provides support for both the
CMSIS-DAP available via USB and the Cortex+ETM connector
on J5. The configuration also contains DDR and clock init code
hooked into the reset-init event handler.
Change-Id: I68303e0038e137dcadc57525e662428769fb69f2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3564
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Chip ID and flash layout taken from
Atmel-11102F-ATARM-SAM4C32-SAM4C16-SAM4C8-SAM4C4-Datasheet_27-Mar-15
and tested on a SAM4C32-EK (rev A).
Change-Id: I68aae5b60994c0b5964ea9031d40bc76ba025675
Signed-off-by: Owen Kirby <oskirby@gmail.com>
Reviewed-on: http://openocd.zylin.com/3527
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
target tcl to enable debugging of ARM Cortex-A5 on ADSP-SC58x
Change-Id: I378f8b94b7d6d6b9d0567985abc0e36aea7c8dea
Signed-off-by: Peter Lawrence <majbthrd@gmail.com>
Reviewed-on: http://openocd.zylin.com/3125
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Remove comment about workaround of not working 'reset halt' - not needed
as 'reset halt' is working as expected @ EDBG with srst_only.
Add srst_pulls_trst to reset_config as it no more triggers an error.
Change-Id: I47cf445690c46ccfb866900cddbfcaefc8649f82
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3722
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Purge all legacy interface configurations so there's no more confusion
over which one to use.
Also remove doc/INSTALL.txt which mentions ft2232 but otherwise just
duplicates what INSTALL says.
Change-Id: Ic94f808f123d4917e600b79309f1272c78a7bb11
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3236
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
At least on my (phyCORE-AM335X) system, the AM335x watchdog
needs to be disabled to use OpenOCD for more than 6.5 seconds
after reset.
Change-Id: I3d883a9f572b0ccb92f9864853a00c372e39d7f2
Signed-off-by: Harald Welte <laforge@gnumonks.org>
Reviewed-on: http://openocd.zylin.com/3391
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Instead of updating these regularly we can just accept any IDCODE for the
boundary scan TAP.
The only downside might be that it's not immediately obvious if you
source a config for the wrong type of STM32.
Change-Id: I96d4d81699a491b3a46de3f0d3fd078ffddad4e4
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3385
Tested-by: jenkins
Both boards use SEGGER interface.
nRF52 flash driver is in change 3511.
The board files were needed for transport select to SWD. The default
jtag transport didn't failover to SWD.
Change-Id: Id9c72aa88eeeb6a4e1999ee182f5284dbe535c05
Signed-off-by: Rick Foos <rfoos@solengtech.com>
Reviewed-on: http://openocd.zylin.com/3600
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik.hederstierna@gmail.com>
Reviewed-by: Michael Dietz <mjdietzx@gmail.com>
Reviewed-by: Jiří Pinkava <j-pi@seznam.cz>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The Linksys WAG200G router has a TI AR7 SoC and a 4MB Flash layout
similar to the Netgear DG834v3 router [1].
Below is an example of a successful flash recovery, using a TUMPA,
connected to the MIPS EJTAG 2.6 header (JP102) of the router.
WAG200G [2] TUMPA [3]
Desc Pin Pin Desc
------------------------
nTRST 1 3 nTRST
TDI 3 5 TDI
TDO 5 13 TDO
TMS 7 7 TMS
TCK 9 9 TCK
nSRST 11 15 RST
GND 2 4 GND
Note that nSRST is optional to halt the CPU, but is required to probe
the flash. For instance, recover the kernel with:
$ sudo ./src/openocd -s tcl \
-f interface/ftdi/tumpa.cfg \
-f tools/firmware-recovery.tcl \
-c 'board linksys-wag200g;
reset_config srst_only;
flash_part kernel /path/to/kernel.bin;
shutdown'
[1] https://wiki.openwrt.org/toh/linksys/wag200g
[2] https://www.linux-mips.org/wiki/JTAG#JTAG_headers
[3] http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual#20_PIN_JTAG_Connector
Change-Id: I952ba9f706e2e4f8f95ca03a5fa58f391ca030b6
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Reviewed-on: http://openocd.zylin.com/3776
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Kinetis driver checks MDM STAT register to detect secured state of MCU.
Original version often reported a blank device as secured one.
Change #3010 has not fixed all false reports.
After changes in arm_adi_v5 infrastructure secured devices was not detected
at all.
New algorithm uses multiple MDM STAT reads and counts MDM_STAT_SYSSEC and
MDM_STAT_FREADY bits. Both secured MCU and MCU locked-up in RESET/WDOG loop
are detected reliably.
Detection is run in both kx.cfg and klx.cfg from examine-start event,
not examine-end as before. Event is configured only for non hla adapter.
Minor fix in klx.cfg: commented out adapter_khz 24000 in reset-init.
Such frequency is not supported in VLPR CPU mode and with JTAG.
Change-Id: I2ec2b68c45bde9898159cd15fbdcbcfa538c41d9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3547
Tested-by: jenkins
Reviewed-by: Steven Stallion <stallion@squareup.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
XDS100v3 is software compatible with the XDS100v2, but has a
different usb pid. This commit adds `xds100v3.cfg` that sources
the v2 one and changes the usb pid.
Change-Id: Ie29d325e8992d2de2f97d70862beeb63932ffa80
Signed-off-by: Remco Bloemen <openocd-gerrit@xn--2-umb.com>
Reviewed-on: http://openocd.zylin.com/3632
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
MBFTDI is a very cheap FT2232-based JTAG adapter
for programming Marsohod FPGA board.
Please see http://www.marsohod.org/prodmbftdi for details.
Change-Id: I35f758b49d1566098dc27f9581829cccad93ceeb
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-on: http://openocd.zylin.com/3604
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Increase workareasize when it is know we have a larger device.
Change-Id: Ieaee92e7cd25cc201989f14de122349698871412
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3378
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
PSoC4 design prevents reset halt/init with standard/low level
SWD adapter if hw reset line configured. Give user hint
to use 'reset_config none' in such case.
Change-Id: I0ca2c46b8575829b0013fd151f2eb63963d66653
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3617
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The IDCODE of Artix7 15T in the UG470 is wrong; Artix7 35T and 15T don't have the same IDCODE.
I've tested this on real hardware.
Change-Id: Iac267dc449c23454dd119126749dbeb8267c18ac
Signed-off-by: Felix Held <felix-openocd@felixheld.de>
Reviewed-on: http://openocd.zylin.com/3633
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Allow using physical addresses with mem2array and array2mem. In order
to minimize the impact on existing scripts, "phys" is added as an
optional 5th parameter to both commands.
This patch also adds "phys" variants to the memwrite/memread commands
in memory.tcl.
Change-Id: Ia6307f9d861789e7f3ccf1f98961d666bf8d85d6
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3387
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
add "mrb" command to read a byte of memory into a variable
Change-Id: I5ddc9fbcc55958a249548627bd15824df6dc0d61
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3542
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Just like observed with the General App Kit earlier, it now started to
fail halting:
SWD IDCODE 0x2ba01477
TARGET: xmc4500.cpu - Not halted
in procedure 'reset'
in procedure 'ocd_bouncer'
SWD IDCODE 0x2ba01477
Halt timed out, wake up GDB.
Rely on the target's default sysresetreq behavior to allow flashing to
work seemlessly again.
Change-Id: Ib9ce5f2c0ab99dca6d0fc74435fe26a58437fae5
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3416
Tested-by: jenkins
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested with TI MSP-EXP432P401R LaunchPad, via both on-board XDS110-ET (swd)
and external J-Link (jtag).
Change-Id: Ic0caa8516a155754b1c88a04acc8d3c511d9a5f7
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3485
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The current configuration leads to the following error when trying to
program the target:
SWD IDCODE 0x2ba01477
timed out while waiting for target halted
TARGET: efm32.cpu - Not halted
in procedure 'program'
in procedure 'reset' called at file "embedded:startup.tcl", line 478
in procedure 'ocd_bouncer'
Use the default reset handling of the target (SYSRESETREQ) to reset the
system rather than SRST to fix the problem.
Tested on EFM32GG, EFM32TG and EZR32WG STK.
Change-Id: I788c41baf08b20814cbe0934b563424c4bc144b8
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3420
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn
or CortexXn. Further it's Cortex-M0+, not M0plus.
Cf. http://www.arm.com/products/processors/index.php
Consistently write it the official way, so that it stops propagating.
Originally spotted in the documentation, it mainly affects code comments
but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output.
Found via:
git grep -i "Cortex "
git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu"
git grep -i "CortexM"
Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3483
Tested-by: jenkins
Reviewed-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Both the STM32F429I-DISC{O,1} boards are equipped with the same MCU, but
differ by the debugging chip:
- the STM32F429I-DISCO uses the ST-LINK/V2 chip;
- the STM32F429I-DISC1 uses the ST-LINK/V2-B chip (which matches the USB
VID/PID set in stlink-v2-1.cfg).
Change-Id: I07d637f72d26cf5d714472638da974eb6ca02325
Signed-off-by: Samuel Martin <s.martin49@gmail.com>
Reviewed-on: http://openocd.zylin.com/3492
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The XMC1000 family uses a very different flash interface from XMC4000.
Tested on XMC 2Go and XMC1100 Boot Kit.
Change-Id: I3edaed420ef1c0fb89fdf221022c8b04163d41b3
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3418
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested-by: jenkins
Tested with MKE04Z8VTG4, MKE02Z64VLC4 and MKE02Z64VLD2.
Change-Id: I606e32a2746a3b96d3e50f3656ba78d40c41c1ea
Signed-off-by: Ivan Meleca <ivan@artekit.eu>
Reviewed-on: http://openocd.zylin.com/3380
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Leading zeros for the serial number are not necessary anymore.
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Change-Id: Ie4ff47b9cda7ccf314c6fda9a2784947db5ee4d9
Reviewed-on: http://openocd.zylin.com/3401
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The Spansion FM4 family of microcontrollers does not offer a way to
identify the chip model nor the flash size, except for Dual Flash vs.
regular layout. Therefore the family is passed as argument and
wildcard-matched - MB9BFx6x and S6E2CC families are supported.
Iterations showed that ...
1) Just doing the flash command sequence from SRAM loader code for each
half-word took 20 minutes for an 8 KB block.
2) Doing the busy-wait in the loader merely reduced the time to 19 minutes.
3) Significant performance gains were achieved by looping in loader code
rather than in OpenOCD and by maximizing the batch size across sectors,
getting us down to ~2 seconds for 8 KB and ~2.5 minutes for 1.1 MB.
(Tested with SK-FM4-176L-S6E2CC-ETH v11, CMSIS-DAP v23.)
gcc, objcopy -Obinary and bin2char.sh are used for automating the
integration of hand-written assembler snippets.
Change-Id: I092c81074662534f50b71b91d54eb8e0098fec76
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2190
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The reset-init hook for this target speeds up the CPU clock and JTAG adapter
speed. When the target is reset running with high adapter speed, a series of
warnings "DAP transaction stalled (WAIT) - slowing down" will be generated
since the adapter speed is not reduced to fit the slower CPU speed.
Fix: reduction of the adapter speed before a reset is performed.
Change-Id: Iabfc8e3f70311e0e71c8eed09b8a37fcbed9c58d
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3365
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add support for the Intel Quark mcu D2000 using the new quark_d2xx
target.
Changes to the lakemont part are needed for the D2000 core and
backwards compatible with the X1000 one.
Change-Id: I6e1ef5a5d116344942f08e413965abd3945235fa
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/3199
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
niietcm4_write() buffer padding:
add correct buffer padding for 16 bytes.
Args check in FLASH_BANK_COMMAND_HANDLER():
first version of the driver had 7 args, current - 6. This patch will fix
error when flash is rejected (current k1921vk01t.cfg has flash bank init
with 6 args).
Timeouts in flash flag checking procedure:
increase timeouts in niietcm4_opstatus_check() and niietcm4_uopstatus_check()
cause there were problems in some hardware configurations.
JTAG ID:
wrong id in k1921vk01t.cfg replaced with right one.
Signed-off-by: Bogdan Kolbov <kolbov@niiet.ru>
Change-Id: I84296ba3eb4eeda4d4a68b18c94666f1269a500f
Reviewed-on: http://openocd.zylin.com/3171
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This patch fixes the tap order so that it matches the actual jtag
chain when all taps are enabled. It also introduces a variable
DEFAULT_TAPS that can be set outside of this script, e.g. on the
command line, to specify which taps are to be enabled on init.
Lastly, a new debug target "am335x.m3" is added so that the Wakeup-M3
can be selected for debugging.
Change-Id: Iccf177fda8d5e3737b1b2bb8fd1eaa7d3262ed9f
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3013
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested with "J-Link OB RX621-ARM-SWD V1 compiled Nov 4 2014 10:47:22".
Change-Id: Ib64c0be407f99df57f058a4498556fd5ab7e9112
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3170
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested with Relax Kit for 5V Shields:
J-Link Lite-XMC4200 Rev.1 compiled Oct 14 2015 10:14:50
and with Relax Lite Kit:
J-Link Lite-XMC4200 Rev.1 compiled Oct 14 2015 10:14:50
Derived from xmc4800-relax.cfg.
Change-Id: I4e10fb6ed1f85168634d3b5259d3041ffc6b74d8
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3130
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds docs, example config, flash driver.
Driver is only supports K1921VK01T model for now.
Change-Id: I135259bb055dd2df1a17de99f066e2b24eae1b0f
Signed-off-by: Bogdan Kolbov <kolbov@niiet.ru>
Reviewed-on: http://openocd.zylin.com/3011
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Base config without flash support for now.
Change-Id: I96a5b6ad35e00dc706177ea9dbdffc384ae7f62b
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3110
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The pflash.0 bank should not be present as it overlaps with
the flash bank created by target/kx.cfg, triggering an error.
This is also in line with the existing twr-k60f120m.cfg.
Change-Id: I5f620e01319d967f12e029fb6865ccdd031713b3
Signed-off-by: Jonathan Larmour <jifl@eCosCentric.com>
Reviewed-on: http://openocd.zylin.com/3108
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Atmel introduced a "Device Service Unit" (DSU) that holds the CPU
in reset if TCK is low when srst (RESET_N) is deasserted.
Function is similar to SMAP in ATSAM4L, see http://openocd.zylin.com/2604
Atmel's EDBG adapter handles DSU reset correctly without this change.
An ordinary SWD adapter leaves TCK in its default state, low.
So without this change any use of sysresetreq or srst
locks the chip in reset state until power is cycled.
A new function dsu_reset_deassert is called as reset-deassert-post event handler.
It optionally prepares reset vector catch and DSU reset is released then.
Additionally SWD clock comment is fixed in at91samdXX.cfg and clock is
lowered a bit to ensure a margin for RC oscillator frequency deviation.
adapter_nsrst_delay 100 is commented out because is no more necessary after
http://openocd.zylin.com/2601
Change-Id: I42e99b1b245f766616c0a0d939f60612c29bd16c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2778
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
16000kHz is only safe after PLLs have been locked
properly. Until that's done (with reset init), we
can only safely run at 1000kHz.
Change-Id: I4e0a17e88aa9919cd6c34d44da68e23115c0d3a3
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/3015
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Added interface config file for the FTDI FT232H based UM232H module.
This should work with UM232H-B too, an even cheaper module, but
that has not been tested.
Change-Id: Ifc312d6741da0b7862fe07d854023190d7afe251
Signed-off-by: Ragnar Sundblad <raggesu@gmail.com>
Reviewed-on: http://openocd.zylin.com/3031
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Keep clocks running in low power modes. Stop watchdogs from interfering
with the debug session. Set up PLL and increase clock at reset init.
Change-Id: I232d769d893d54e4ea9411c46c56b19587b69919
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2707
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This is a complete flash driver for the Infineon XMC4xxx family of
microcontrollers, based on the TMS570 driver by Andrey Yurovsky.
The driver attempts to discover the particular variant of MCU via a
combination of the SCU register (to determine if this is indeed an
XMC4xxx part) and the FLASH0_ID register (to determine the variant).
If this fails, the driver will not load.
The driver has been added to the README and documentation.
Tests:
* Hardware: XMC4500 (XMC4500_relax), XMC4200 (XMC4200 enterprise)
* SWD + JTAG
* Binary: 144k, 1M
Note:
* Flash protect only partly tested. These parts only allow the flash
protection registers (UCB) to be written 4 times total, and my devkits
have run out of uses (more on the way)
Future Work:
* User 1/2(permalock) locking support via custom command
* In-memory flash loader bootstrap (flashing is rather slow...)
Change-Id: I1d3345d5255d8de8dc4175cf987eb4a037a8cf7f
Signed-off-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2488
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This is a driver for the Atmel Cortex-M7 SAMV, SAMS, and SAME.
I started with the at91sam4.c driver and then restructured it
significantly to try to simplify it and limit the functionality
to just a flash driver, as well as to comply with the style guide.
Change-Id: I5340bf61f067265b8ebabd3adad45be45324b707
Signed-off-by: Morgan Quigley <morgan@osrfoundation.org>
Reviewed-on: http://openocd.zylin.com/2952
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested with cmsis-dap using the EDBG chip on the board.
Change-Id: I3d398685c81e4701a9f6c1a66e60f7a87f839daa
Signed-off-by: Morgan Quigley <morgan@osrfoundation.org>
Reviewed-on: http://openocd.zylin.com/3092
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
New configuration for NXP LPC4370 which consists of a Cortex-M4
and two Cortex-M0 cores.
Change-Id: I9918e3ff33218a14a99e4bbab9dce2e7b45b4d96
Signed-off-by: Jim Norris <u17263@att.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2124
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This reverts commit 7d7a43fd36.
The change concerns the "Black" variant of the TI BeagleBone, while the
configuration file is for the original BeagleBone board, which actually
embeds a debug interface on the PCB.
Change-Id: I2232af210deb698f8b3c0a547f26cd0a0a8f89d0
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3094
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Add configs for Atheros ar2313 MIPS based WiSoC and
board based on this chip: La Fonera FON2200
Change-Id: Ibfdbfc9c2beca6cf436c9ee5e493b08bfb55ac85
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2839
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add configs for Atheros ar2313 MIPS based WiSoC and
board based on this chip: Netgear WP102
Change-Id: Id93957b5d5851a272f15be35f9f448a9ce6d8a08
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2835
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Since 2cbbe9a it was actually decreasing the configured work area size.
We could now do "set WORKAREASIZE 0x2000" before sourcing lpc4350.cfg,
but there seems no point in doing so. Simply drop the configuration here.
Change-Id: I25b9dbbc007ba652b66099832198b7c329929858
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3086
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Default to lpc8xx as before, but allow setting the actual CHIPNAME.
Change-Id: I5a48fa75c640440a0d4c3f2858653e94bed846d2
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3084
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Board files should not select the interface. The BeagleBone Black is not
limited to just one JTAG interface.
Change-Id: I71ccc3dd9e2ca331a436701fab04e548b0abf829
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3083
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Adapted from diolan_lpc4350-db1.cfg. Both boards are identical except
for the SoC, so keep them in sync.
Change-Id: If892d8e953b0e3a9209a95b3b23a547357c10b7a
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3038
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reuse the flashless LPC4350 as base and amend it as necessary.
The LPC43x7 have 2x 512 KB of flash.
Change-Id: Ia7ffbc7101023479971984b839f171ed4be6b089
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3037
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Add support for the JTAG TAPID found on SK-FM4-U120-9B560-MEM V1.1.0 board.
Change-Id: Idbfe28927e0c549f0c89c29904d23971281927c9
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3039
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
It is found on the SK-FM4-U120-9B560-MEM V1.1.0 among others.
Change-Id: I4c708c9391e954cbbc8d0860a2a2dbd264aea865
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3008
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Its memory layout is different from MB9BFxxx.
Change-Id: I39c9f9cf582cd182971a9f83bb88c7a18da6cf15
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3007
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The xCORE-XA Core Module board has an XS1-XAU8A-10 SoC with 8 xCORE cores
and one ARM core. This config is for the ARM Cortex-M3, via J-Link OB.
Tested with "J-Link OB-STM32F103 V1 compiled Feb 5 2014 13:48:52".
Change-Id: Id7fadf8f323b45d5cfc0cae1054bd7b916771d6a
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2763
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The XS1-XAU8A-10 has 8 xCORE cores and one ARM core.
This config represents the ARM Cortex-M3 core, which is apparently
Silicon Labs EFM32 Giant Gecko IP.
Change-Id: I998360f096c759d2e274d96c1ca2e0450ba61146
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2762
Tested-by: jenkins
Reviewed-by: Oleksij Rempel
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Most Xilinx FPGA devices contain an embedded, unique device identifier
called the "Device DNA". The identifier is nonvolatile, permanently
programmed into the FPGA, and is unchangeable providing a great serial
/ tracking number.
Debugging was done in https://github.com/timvideos/HDMI2USB/issues/36
Change-Id: Iad03eafb40887f0321a4dc22858a7c3bf37a12b3
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2960
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Another board supported by the ixo-usb-jtag project.
Change-Id: I676197c64e208886bc03d1bafcc964ef1fc2160b
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2963
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The board is supported via the ixo-usb-jtag firmware.
Change-Id: I1e8a5ead850c0843b8532a5b54a7e7117778278e
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2962
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Also add further documentation about the project and how to use it.
Change-Id: Ia9878de566b3c8c1ea29f129287d5aea904d861d
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2961
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Flash driver "mini51.c" and "nuc1x.c" are same target MCU.
This patch integrates each driver and functions,
and makes into new "NuMicro" flash driver.
Change-Id: Ifff5c1cfdd265acca0f489631695be9194fa144c
Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-on: http://openocd.zylin.com/2794
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
A target config and a simple flash driver for the ADuCM360 microcontroller.
The EEPROM of the chip may be erased and programmed.
Change-Id: Ic2bc2f91ec5b6f72e3976dbe18071f461fe503b8
Signed-off-by: Ivan Buliev <i.buliev@mikrosistemi.com>
Reviewed-on: http://openocd.zylin.com/2787
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
Tested with Porcupine-1 JTAG adapter board and Digilent JTAG-HS3 interface;
reset does not yet work, pending nSRST configuration of the interface used.
Change-Id: I0d0679e098d93ffbd1539004cdb900e2a8ae4a25
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2730
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
As found on the Parallella-I board SKU A101020.
Change-Id: Ie7e7a36325926d67fbe555b46a9be8a74fac8dba
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2729
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Derived from tcl/interface/digilent-hs1.cfg.
JTAG-HS3 has an open drain buffer on pin 14 for SRST to work with
PS_SRST_B on Xilinx Zynq SoC.
Change-Id: I1e9e72d0511528a61207e318aff937ae9fad5bf9
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2728
Tested-by: jenkins
Reviewed-by: Robert Jordens <jordens@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Added support for SWD transport similar to sysfsgpio driver.
Added configurable peripheral base address to support Raspberry Pi 2.
Change-Id: If76d45fbe74ce49f1f22af72e5f246e973237e04
Signed-off-by: Christoph Pittracher <pitt@segfault.info>
Reviewed-on: http://openocd.zylin.com/2802
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add the chip IDs corresponding to the new 5V "SAMC" parts which are
otherwise identical to the SAMD and should work with this driver. Also
add the configurations for their Xplained Pro boards.
Change-Id: Ic268d4ac384a3a77d4211a94da9f9faf4d8c0f7b
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2809
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The Pipistrello is a low cost FPGA board with a Xilinx
Spartan6 LX45, a SPI flash and onboard FTDI JTAG.
This board is a good example use case for the jtagspi
flash driver talking through a proxy bitstream.
Change-Id: I04a80610ff825c36ebcb67b879507028eed141ad
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2846
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Many FPGA board speak JTAG and have a SPI flash for their bitstream
attached to them. The SPI flash is programmed by first uploading a
proxy bitstream to the FPGA that connects the JTAG interface to the
SPI interface if the IR contains a certain USER instruction. Then the
SPI flash can be erase, written, read directly through the JTAG DR.
The JTAG and SPI signaling is compatible. Such a proxy bitstream only
needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the
chip select when the IR contains the special instruction and the JTAG
state machine is in the DR-SHIFT state.
Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2844
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This covers only the Cortex-A5 for now, not the Cortex-M4.
Change-Id: I739ec52b14b83d6e9f124ed61f8941502e481402
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2766
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
code polishing to be consistent with other scripts
Change-Id: Ib52a92f48df9d2bdf543792b856e33aa04dbebe3
Signed-off-by: Radek Dostal <radek.dostal@streamunlimited.com>
Reviewed-on: http://openocd.zylin.com/2779
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reset stopped working with this setting.
Change-Id: I98e8fafa48e0ab65dce8110870be422edf7b2fdb
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2727
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Split TMS570 target into LS31/LS21 and LS20/LS10 targets.
Board for the TMS570LS20SUSB Kit, which uses the TMS570 Cortex-R4 MCU from TI.
Tested attaching.
Change-Id: I1a69ac1ed800d0d6b7f9860c19cbd149e3e47620
Signed-off-by: Alex Ray <a@machinaut.com>
Reviewed-on: http://openocd.zylin.com/2089
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds support for the new Atmel SAML21 family of low-power Cortex
M0+ devices. Their Flash controller is essentially the SAMDxx one so
the change consists of adding the new part IDs. Unfortunately the
device ID logic had a couple of mistakes in it that did not affect
anything on SAMD2x devices (due to 0 values expected there) but that is
a problem on L21, it's therefore addressed here and things should now
match the datasheets.
Tested on Amtel SAML21 Xplained Pro development kit against the included
SAML21J18A there. Also tested for regressions on a SAMD20 and SAMD21
using their dev kits.
Change-Id: I768f75e064b8656c15148730dacaa4c3acfc4101
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2690
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Use mmw to manipulate only selected bits of the word. msb and mwb verify the
memory location and may error on PLLRDY set as a result of PLLON written.
Change-Id: I9a4c1e58f002a1e5e99be1bd34aac27ba65d111d
Reported-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2702
Tested-by: jenkins
GP and EPOS EVMs do not provide xds100v2 on board,
rather they have a pin header which can be used
to attach any debug pod the user might want.
Change-Id: I61678c50900fbe0fab500ea42f85ecde7a490ded
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2618
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This is a remake of http://openocd.zylin.com/1966
originally written by Angus Gratton <gus@projectgus.com>
ATSAM4L has a "System Manager Access Port" (SMAP) that holds the CPU
in reset if TCK is low when srst (RESET_N) is deasserted.
Without this change any use of sysresetreq or srst locks the chip
in reset state until power is cycled.
A new function smap_reset_deassert is called as reset-deassert-post event handler.
It optionally prepares reset vector catch and SMAP reset is released then.
Change-Id: Iad736357b0f551725befa2b9e00f3bc54504f3d8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2604
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Also some hints around deprecated tcl/interface/turtelizer2.cfg added.
Change-Id: Ifa57b49febffaeddd5d8ff0a48833d3544927b10
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2584
Tested-by: jenkins
Reviewed-by: Harald Kipp
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Works best after update to firmware v2.3.
Change-Id: Id2d3a0ae28bba014ee5338df9280fe39773c3398
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2570
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Assembled by trial-and-error for an S6E2CC.
Change-Id: I317c12d24c9075ce3de286455fa3ee45731c5c81
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2569
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Original submitted code had only been tested with em358, but testing with
actual em357 revealed errors that this patch corrects.
Change-Id: I70cf31210de8ed84e3755a56e76261ad200322bb
Signed-off-by: Ed Beroset <beroset@ieee.org>
Reviewed-on: http://openocd.zylin.com/2581
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
When using ppdev driver 0 is the most appropriate default value as it
corresponds to /dev/parport0. Raw port address is suitable only for
direct access (I think that's parport-giveio on windows).
Reported by danitool on IRC.
Change-Id: I983c22251de6601b433ad31aaf660fb664cee7e9
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2572
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested with "J-Link Lite-XMC4000 Rev.1 compiled Dec 7 2012 19:23:07"
on XMC4500 Relax Lite Kit V1.
Change-Id: Ib680a444fa4cadbf640afba15d607c0e6bd4ab2c
Signed-off-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2567
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Base config, verified against XMC4500, XMC4400 and XMC4100/XMC4200 manuals.
Change-Id: I10907bdf307bc6d11dc5454bf5391758de49dc30
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2480
Tested-by: jenkins
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
this is just to avoid open coding that in
icepick_d_tapenable. Cleanup only, no functional
changes.
Change-Id: Iabd20291b7bdd95957afa1c74f52171789201227
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2624
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
it also works on icepick_d.
Change-Id: I50c0c81286aae673c94ea77e47454ff48eab1668
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2623
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reusing what's already there to ease maintainability.
Change-Id: I2030581669c644e2d9d9f9968075ab6344445d04
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2622
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is only for the sake of completeness as
default coreid is zero. In any case, coreids 1-4 are
used for the different PRU cores inside the SoC.
Change-Id: I775f2f444b1a908ffaf7bdbc43bcc966f19668c4
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2621
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Use more descriptive names for JRC and DAPs
so they more closely match documentation.
For example there's no Cortex A9 DAP, that's
the DebugSS DAP where Cortex A9 target sits. In
that same DAP we have have ETM, STM and both
dual-PRU subsystems.
Change-Id: I0e66ebb6299763f96606fae3e4c62e5785c804f2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2620
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Main DAP (where Cortex A9 sits) ID is actually
0x46b6902f. Fix it.
Change-Id: Ifa3335186bcf60d264d4ecea477bfe2f5ca10ead
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2619
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Add support for Texas Instruments AM437x
Industrial Development Kit support.
Change-Id: I33ed71c7392c3805a86cf2c8adce83c0e8aa323d
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2617
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
this event handler will configure and lock PLLs
and configure DDR so platform is placed in usable
state.
Change-Id: Idd02f4c9789181d69578f8606ac3576ea1dd8a0b
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2616
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
sometimes, watchdog might be left running and
it could expire in the middle of a debug session,
to prevent that, just make sure to disable watchdog
on reset-end if current state is 'halted'.
Change-Id: Ib4f2a2321cba17cd8c56ca3ae63114a563a6de90
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2615
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
a later commit will implement a proper reset-init
handler to lock pll and configure ddr as we should.
Change-Id: I432cf28a5a944bfa83c20aed7298dbd29df30e38
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2614
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
xds100v2 asks us to call these three commands to
guarantee proper behavior, so do it.
Change-Id: Iecf9c148ce7c2082ef915b46eeb511ceea395cc3
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2613
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
default already is jtag, but this silences a
warning during startup.
Change-Id: I94478327bbb259649500ef74a5b5c10d51e2a517
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2612
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
According to AM4379 TRM [1], table 2-1 L3 Memory Map,
we have a total of 256KiB and there's no reason not to
use it all.
[1] http://www.ti.com/lit/ug/spruhl7b/spruhl7b.pdf
Change-Id: I117f2afe721bc4e3f0df304d3542e1a91aa69d12
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2611
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Since commit ec9ccaa288 (arm_adi_v5: make dap_lookup_cs_component()
traverse subtables and handle multicore) AM437x devices can't be used
with OpenOCD anymore. The reason is that dbgbase used to be set to zero
before that commit and that just happens to work with AM437x devices.
A more robust solution is to pass correct dbgbase when creating the
target, which this commit does.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Change-Id: Iaf2617804324de8094b25137943e08b84f14c75f
Reviewed-on: http://openocd.zylin.com/2602
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This should allow most of the existing configurations for older
versions to remain compatible without forcing the user to change his
or her config to explicitly select transport.
Also in some circumstances can remove the need to chain a "-c transport
select X" when building custom configs on the command line, which seems
like a common new user pitfall.
Change-Id: Ic87a38c0b9b88e88fb6d106385efce2f39381d3d
Suggested-by: Petteri Aimonen <jpa@git.mail.kapsi.fi>
Signed-off-by: Angus Gratton <gus@projectgus.com>
Reviewed-on: http://openocd.zylin.com/2551
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Valgrind-tested.
Comparison of flashing performance on an FRDM-KL25Z board running mbed
CMSIS-DAP variant, 5MHz clock, old driver:
wrote 28096 bytes from file demo.elf in 26.833590s (1.023 KiB/s)
verified 27264 bytes in 1.754972s (15.171 KiB/s)
this implementation:
wrote 28096 bytes from file demo.elf in 3.691939s (7.432 KiB/s)
verified 27264 bytes in 0.598987s (44.450 KiB/s)
Also tested "Keil ULINK-ME CMSIS-DAP" with an STM32F100 target, 5MHz
clock, results reading from flash, old driver:
dumped 131072 bytes in 98.445305s (1.300 KiB/s)
this implementation:
dumped 131072 bytes in 8.242686s (15.529 KiB/s)
Change-Id: Ic64d3124b1d6cd9dd1016445bb627c71e189ae95
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2356
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Since the very first flash bank is already defined in target/kx.cfg,
there's no sense in repeating it.
Reported and tested by Richard Braun.
Change-Id: I417b7072b5e6675ddbf824446e7581b8b7da8f4b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2595
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This provides support for various trace-related subsystems in a
generic and expandable way.
Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2538
Tested-by: jenkins
Keep clocks running in low power modes. Stop watchdogs from interfering
with the debug session. Set up PLL and increase clock at reset init.
Change-Id: I984d2018f7d47a1042f1e12894563154fa7b566c
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2196
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The signal names are changed for consistency with TI's docs and
sources.
Change-Id: Ic5c5314daa20f6f610be8a848399f951d47aa137
Signed-off-by: Matthijs van Duin <matthijs@rinnic-vaude.nl>
Reviewed-on: http://openocd.zylin.com/2231
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Initial Support for AT91SAM7A2 on Olimex SAM7-LA2 board.
The board seems not to be able to reset into halted mode, as srst is
connected to NRESET of the cpu (configured srst_pulls_trst).
JTAG RCLK is connected to CLK.
Tested with interface/ftdi/olimex-arm-usb-ocd-h.cfg.
Change-Id: I2bdd67e3683e45f1119c5850bad294aa107891d8
Signed-off-by: Arne Wichmann <arne.wichmann@gmail.com>
Reviewed-on: http://openocd.zylin.com/2318
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The F334 disco board has a stlink V.2-1 as F3 nucleo boards. Normal F3 disco
boards use stlink v2 and can't ne used.
Change-Id: I77ebef93b184592f25ff18bb2da776d636f60ff0
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2434
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds configs for Alphascale asm9260t ARM based SoC and
Evaluation Kit based on this chip.
Change-Id: Id8d3a1ef204e3ae84540c2693e3d62650ba82f73
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2515
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The flash definition belongs in the target cfg. Add some working area
and suitable reset_config.
Make kx.cfg more similar to klx.cfg.
Disable rclk as it is dead slow and a fixed 1MHz clock seems to work.
Change-Id: I8328f179c3a33be64403da93616abb48651bdfe6
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2227
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Configure the LED to be off by default, blink on activity.
Change-Id: I8515ee66c49bddf866268b85811be15c2dbc086c
Signed-off-by: Anton Kuzmin <anton.kuzmin@cs.fau.de>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2539
Tested-by: jenkins
This is a new driver for Silicon Laboratories SiM3 microcontroller
family, based on the work of Ladislav Bábel. The driver will try to
detect the type of MCU from the device id register, and if this
fails it will use the flash size from the flash bank command.
Driver added to the documentation and to the README.
TCL script added.
Tests:
* Hardware: SiM3C166 (pre-production) and SiM3U167
* Binary: 4kb, 197kb, 256kb
* Flash protect not tested
Change-Id: I701e0cf505ca8ad99be7f83543fe5055b2f65dcc
Signed-off-by: Andreas Bomholtz <andreas@seluxit.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2078
Tested-by: jenkins
Add serial option to jlink config commands, handy when there is more than one
adapter connected.
To select adapter 0123456 for OpenOCD, use
jlink serial 0123456
Change-Id: Ib29ce3f0c4975e1169211721a4531bf4db61f1ee
Signed-off-by: Joerg Fischer <turboj@gmx.de>
Reviewed-on: http://openocd.zylin.com/2521
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds the board to the list of supported devices for the easy
recovery procedure. Only ram_boot is supported for this target.
Change-Id: I144e1836f8b6257e96a42c98c2668da74ce243f6
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2520
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Add configs for Atheros ar9331 MIPS based WiSoC and
board based on this chip: TP-LINK TL-MR3020
Change-Id: I9e99719bce4bbb28311f6e9cddb32288db6e7b91
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2519
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
adds flash support for Nuvoton M052, M054, M058, M0516 microcontrollers
into the mini51 driver, patch also adds support for programing LDROM,
flash data and flash config.
I've tested it on a M0516LBN microcontroller using an ST-LINK/V2:
1. removing security lock:
openocd -f interface/stlink-v2.cfg -f target/m051.cfg -c "init ; halt ; mini51 chip_erase; exit"
2. flashing:
openocd -f interface/stlink-v2.cfg -f target/m051.cfg -c "program file.hex"
Change-Id: I918bfbb42461279c216fb9c22272d77501a2f202
Signed-off-by: Pawel Si <stawel+openocd@gmail.com>
Reviewed-on: http://openocd.zylin.com/2426
Tested-by: jenkins
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Added support for the Cortex-M3 based TI low power RF SoC CC2538 and
the CC26xx family.
These chips need a start sequence for switching from cJTAG to JTAG
before being used with OpenOCD, this is done in the tcl proc
ti_cjtag_to_4pin_jtag in the ti-cjtag.cfg config.
The configs for CC2538 and CC26xx run the start sequence on post-reset
event and set the ICEPick IDCODE in the data register for OpenOCD to
read, this is done so that every time OpenOCD resets the device, it
will enable JTAG.
Change-Id: I7db620211c0e7e03fad59d24fe31d23a9cdcfedc
Signed-off-by: Jacob Palsson <jaaacke@gmail.com>
Reviewed-on: http://openocd.zylin.com/2232
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This patch adds support for Silicon Labs (formerly Ember) EM357
and EM358 chips and derivatives.
Change-Id: Ie63aed95a2f4ef1a6b955e301a51b4de1b3a5462
Signed-off-by: Ed Beroset <beroset@ieee.org>
Reviewed-on: http://openocd.zylin.com/2470
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
New NOR flash driver was derived from stm32lx.
Procedure ocd_process_reset_inner is overriden in psoc4.cfg
to handle reset halt and system ROM peculiarities.
Change-Id: Ib835324412d106ad749e1351a8e18e6be34ca500
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2282
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds a trivial config for LPC8xx chips based on the already
existing infrastructure in lpc1xxx.cfg.
Change-Id: I7384df1f3c2e3e8ab767319728db5c4f8149480f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2464
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Added support for the ST nucleo l152re board with a stm32l152ret6 MCU,
analog to st_nucleo_f* configurations.
Change-Id: Id2c61dc7a7cb2e1cc64442191b367bab4247bdeb
Signed-off-by: Thomas Eichinger <eicht@lepus.uberspace.de>
Reviewed-on: http://openocd.zylin.com/2489
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
It depends on the particular target whether it can work with SRST
asserted or not, so this belongs to the target config rather than the
board config.
Also, this allows for simple
openocd -f myboard.cfg -c "reset_config connect_assert_srst"
command to be used whenever a user feels a need to connect to an
unresponsive target.
Change-Id: I3d8da9ae47088fc0c75a20bfdd20074be1014de0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2459
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
So remove it from all the configs, it's misleading, and leads to cargo
culting of config files.
Change-Id: I2b77e60d5e96f9759c7c9fc91b20e73be2e95d9a
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2446
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is an integrated adapter used on the IoT-LAB boards.
Schematics are available from
https://github.com/iot-lab/iot-lab/wiki/Docs/openm3-schematics.pdf
Change-Id: I1c80e72653c3f319bb04d01e3dfddb1c2447c398
Tested-by: Quentin Lampin <quentin.lampin@orange.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2415
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
It is derived from ti_tmdx570ls31usb.cfg, using a different TAP ID.
Change-Id: I2d911995c76ea4f75a780cc230d61f4959825809
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2440
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Matthias Welwarsky
Marek Vasut
Niklas Söderlund
Robert Jordens
Tomas Vanek
Matej Kogovsek
Paul Fertser
Mateusz Manowiecki
Michele Sardo
Jonas Norling
Bohdan Tymkiv
Oleksij Rempel
Patrick Stewart
barthess
Pushpal Sidhu
Ake Rehnman
Jiri Kastner
elmot
Alexandre Torgue
Jonathan McDowell
Peter Griffin
Slowcoder
Diego Herranz
Moritz Fischer
Grzegorz Kostka
Forest Crossman
Juha Niskanen
Marc Schink
Jan Čapek
Jerome Lambourg
Matthias Welwarsky
Matthias Bock
Karl Palsson
Uwe Bonnes
Owen Kirby
Andreas Färber
Peter Lawrence
Andreas Fritiofson
Harald Welte
Rick Foos
Vivien Didelot
Sean Cross
Antony Pavlov
Remco Bloemen
Felix Held
Samuel Martin
Ivan Meleca
Alexander Kurz
Freddie Chopin
Andrew Kohlsmith
Ivan De Cesaris
Tim 'mithro' Ansell
Manuel Limones
Bogdan Kolbov
Jonathan Larmour
Felipe Balbi
Ragnar Sundblad
Rémi PRUD’HOMME
Jeff Ciesielski
Morgan Quigley
Jim Norris
Maxime Coquelin
Nemui Trinomius
Ivan Buliev
Christoph Pittracher
Andrey Yurovsky
Radek Dostal
Alex Ray
Spencer Oliver
Ed Beroset
Angus Gratton
Matthijs van Duin
Arne Wichmann
Anton Kuzmin
Andreas Bomholtz
Joerg Fischer
Pawel Si
Jacob Palsson
Heinz Schweiger
Thomas Eichinger
Karl Palsson