interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

stm32xxx.cfg: Only touch IWDG and WWDG in DBGMCU_APB1_FZ. 

Change-Id: Ie0298c8e73bebeccc9346534d63aab4cae49e4f7
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3104
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This commit is contained in:
Uwe Bonnes 2015-11-11 12:54:19 +01:00 committed by Freddie Chopin
parent c3ea15dc62
commit c4b8c74140
5 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tcl/target/stm32f2x.cfg
View File

@ -84,8 +84,8 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
mww 0xE0042008 0x00001800
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
}
$_TARGETNAME configure -event trace-config {

2
tcl/target/stm32f3x.cfg
View File

@ -99,7 +99,7 @@ proc stm32f3x_default_examine_end {} {
mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
# Stop watchdog counters during halt
mww 0xe0042008 0x00001800 ;# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
}
proc stm32f3x_default_reset_init {} {

4
tcl/target/stm32f4x.cfg
View File

@ -96,8 +96,8 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
mww 0xE0042008 0x00001800
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
}
$_TARGETNAME configure -event trace-config {

4
tcl/target/stm32f7x.cfg
View File

@ -80,8 +80,8 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
mww 0xE0042008 0x00001800
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
}
$_TARGETNAME configure -event trace-config {

4
tcl/target/stm32l1.cfg
View File

@ -114,8 +114,8 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
mww 0xE0042008 0x00001800
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
}
$_TARGETNAME configure -event trace-config {