flash/nor/jtagspi: add JTAGSPI driver
Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Robert Jordens
Spencer Oliver
parent
3edcb94186
commit
d25355473d
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@ -0,0 +1,317 @@
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#!/usr/bin/python3
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#
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# Copyright (C) 2015 Robert Jordens <jordens@gmail.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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from migen.fhdl.std import *
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from mibuild.generic_platform import *
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from mibuild.xilinx import XilinxPlatform
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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from mibuild.xilinx.ise import XilinxISEToolchain
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"""
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This migen script produces proxy bitstreams to allow programming SPI flashes
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behind FPGAs. JTAG signalling is connected directly to SPI signalling. CS_N is
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asserted when the JTAG IR contains the USER1 instruction and the state is
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SHIFT-DR.
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Xilinx bscan cells sample TDO on falling TCK and forward it.
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MISO requires sampling on rising CLK and leads to one cycle of latency.
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https://github.com/m-labs/migen
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"""
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class Spartan3(Module):
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macro = "BSCAN_SPARTAN3"
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def __init__(self, platform):
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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spi = platform.request("spiflash")
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shift = Signal()
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tdo = Signal()
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sel1 = Signal()
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self.comb += [
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self.cd_jtag.clk.eq(spi.clk),
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spi.cs_n.eq(~shift | ~sel1),
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]
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self.sync.jtag += tdo.eq(spi.miso)
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self.specials += Instance(self.macro,
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o_DRCK1=spi.clk, o_SHIFT=shift,
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o_TDI=spi.mosi, i_TDO1=tdo, i_TDO2=0,
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o_SEL1=sel1)
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class Spartan3A(Spartan3):
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macro = "BSCAN_SPARTAN3A"
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class Spartan6(Module):
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def __init__(self, platform):
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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spi = platform.request("spiflash")
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shift = Signal()
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tdo = Signal()
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sel = Signal()
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self.comb += self.cd_jtag.clk.eq(spi.clk), spi.cs_n.eq(~shift | ~sel)
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self.sync.jtag += tdo.eq(spi.miso)
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self.specials += Instance("BSCAN_SPARTAN6", p_JTAG_CHAIN=1,
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o_TCK=spi.clk, o_SHIFT=shift, o_SEL=sel,
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o_TDI=spi.mosi, i_TDO=tdo)
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class Series7(Module):
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def __init__(self, platform):
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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spi = platform.request("spiflash")
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clk = Signal()
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shift = Signal()
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tdo = Signal()
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sel = Signal()
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self.comb += self.cd_jtag.clk.eq(clk), spi.cs_n.eq(~shift | ~sel)
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self.sync.jtag += tdo.eq(spi.miso)
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self.specials += Instance("BSCANE2", p_JTAG_CHAIN=1,
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o_SHIFT=shift, o_TCK=clk, o_SEL=sel,
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o_TDI=spi.mosi, i_TDO=tdo)
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self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0,
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i_KEYCLEARB=0, i_PACK=1, i_USRCCLKO=clk,
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i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
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class XilinxBscanSpi(XilinxPlatform):
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pinouts = {
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# bitstreams are named by die, package does not matter, speed grade
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# should not matter.
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# cs_n, clk, mosi, miso, *pullups
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"xc3s100e": ("cp132",
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["M2", "N12", "N2", "N8"],
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"LVCMOS33", Spartan3),
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"xc3s1200e": ("fg320",
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["U3", "U16", "T4", "N10"],
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"LVCMOS33", Spartan3),
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"xc3s1400a": ("fg484",
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["Y4", "AA20", "AB14", "AB20"],
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"LVCMOS33", Spartan3A),
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"xc3s1400an": ("fgg484",
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["Y4", "AA20", "AB14", "AB20"],
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"LVCMOS33", Spartan3A),
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"xc3s1600e": ("fg320",
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["U3", "U16", "T4", "N10"],
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"LVCMOS33", Spartan3),
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"xc3s200a": ("fg320",
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["V3", "U16", "T11", "V16"],
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"LVCMOS33", Spartan3A),
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"xc3s200an": ("ftg256",
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["T2", "R14", "P10", "T14"],
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"LVCMOS33", Spartan3A),
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"xc3s250e": ("cp132",
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["M2", "N12", "N2", "N8"],
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"LVCMOS33", Spartan3),
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"xc3s400a": ("fg320",
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["V3", "U16", "T11", "V16"],
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"LVCMOS33", Spartan3A),
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"xc3s400an": ("fgg400",
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["Y2", "Y19", "W12", "W18"],
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"LVCMOS33", Spartan3A),
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"xc3s500e": ("cp132",
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["M2", "N12", "N2", "N8"],
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"LVCMOS33", Spartan3),
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"xc3s50a": ("ft256",
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["T2", "R14", "P10", "T14"],
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"LVCMOS33", Spartan3A),
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"xc3s50an": ("ftg256",
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["T2", "R14", "P10", "T14"],
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"LVCMOS33", Spartan3A),
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"xc3s700a": ("fg400",
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["Y2", "Y19", "W12", "W18"],
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"LVCMOS33", Spartan3A),
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"xc3s700an": ("fgg484",
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["Y4", "AA20", "AB14", "AB20"],
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"LVCMOS33", Spartan3A),
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"xc3sd1800a": ("cs484",
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["U7", "V17", "V13", "W17"],
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"LVCMOS33", Spartan3A),
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"xc3sd3400a": ("cs484",
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["U7", "V17", "V13", "W17"],
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"LVCMOS33", Spartan3A),
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"xc6slx100": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx100t": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx150": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx150t": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx16": ("cpg196-2",
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["P2", "N13", "P11", "N11", "N10", "P10"],
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"LVCMOS33", Spartan6),
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"xc6slx25": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx25t": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx45": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx45t": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx4": ("cpg196-2",
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["P2", "N13", "P11", "N11", "N10", "P10"],
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"LVCMOS33", Spartan6),
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"xc6slx4t": ("qg144-2",
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["P38", "P70", "P64", "P65", "P62", "P61"],
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"LVCMOS33", Spartan6),
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"xc6slx75": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx75t": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx9": ("cpg196-2",
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["P2", "N13", "P11", "N11", "N10", "P10"],
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"LVCMOS33", Spartan6),
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"xc6slx9t": ("qg144-2",
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["P38", "P70", "P64", "P65", "P62", "P61"],
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"LVCMOS33", Spartan6),
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"xc7a100t": ("csg324-1",
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["L13", None, "K17", "K18", "L14", "M14"],
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"LVCMOS25", Series7),
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"xc7a15t": ("cpg236-1",
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["K19", None, "D18", "D19", "G18", "F18"],
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"LVCMOS25", Series7),
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"xc7a200t": ("fbg484-1",
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["T19", None, "P22", "R22", "P21", "R21"],
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"LVCMOS25", Series7),
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"xc7a35t": ("cpg236-1",
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["K19", None, "D18", "D19", "G18", "F18"],
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"LVCMOS25", Series7),
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"xc7a50t": ("cpg236-1",
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["K19", None, "D18", "D19", "G18", "F18"],
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"LVCMOS25", Series7),
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"xc7a75t": ("csg324-1",
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["L13", None, "K17", "K18", "L14", "M14"],
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"LVCMOS25", Series7),
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"xc7k160t": ("fbg484-1",
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["L16", None, "H18", "H19", "G18", "F19"],
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"LVCMOS25", Series7),
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"xc7k325t": ("fbg676-1",
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["C23", None, "B24", "A25", "B22", "A22"],
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"LVCMOS25", Series7),
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"xc7k355t": ("ffg901-1",
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["V26", None, "R30", "T30", "R28", "T28"],
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"LVCMOS25", Series7),
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"xc7k410t": ("fbg676-1",
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["C23", None, "B24", "A25", "B22", "A22"],
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"LVCMOS25", Series7),
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"xc7k420t": ("ffg1156-1",
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["V30", None, "AA33", "AA34", "Y33", "Y34"],
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"LVCMOS25", Series7),
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"xc7k480t": ("ffg1156-1",
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["V30", None, "AA33", "AA34", "Y33", "Y34"],
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"LVCMOS25", Series7),
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"xc7k70t": ("fbg484-1",
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["L16", None, "H18", "H19", "G18", "F19"],
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"LVCMOS25", Series7),
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"xc7v2000t": ("fhg1761-1",
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["AL36", None, "AM36", "AN36", "AJ36", "AJ37"],
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"LVCMOS18", Series7),
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"xc7v585t": ("ffg1157-1",
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["AL33", None, "AN33", "AN34", "AK34", "AL34"],
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"LVCMOS18", Series7),
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"xc7vh580t": ("flg1155-1",
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["AL28", None, "AE28", "AF28", "AJ29", "AJ30"],
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"LVCMOS18", Series7),
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"xc7vh870t": ("flg1932-1",
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["V32", None, "T33", "R33", "U31", "T31"],
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"LVCMOS18", Series7),
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"xc7vx1140t": ("flg1926-1",
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["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
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"LVCMOS18", Series7),
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"xc7vx330t": ("ffg1157-1",
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["AL33", None, "AN33", "AN34", "AK34", "AL34"],
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"LVCMOS18", Series7),
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"xc7vx415t": ("ffg1157-1",
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["AL33", None, "AN33", "AN34", "AK34", "AL34"],
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"LVCMOS18", Series7),
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"xc7vx485t": ("ffg1157-1",
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["AL33", None, "AN33", "AN34", "AK34", "AL34"],
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"LVCMOS18", Series7),
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"xc7vx550t": ("ffg1158-1",
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["C24", None, "A23", "A24", "B26", "A26"],
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"LVCMOS18", Series7),
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"xc7vx690t": ("ffg1157-1",
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["AL33", None, "AN33", "AN34", "AK34", "AL34"],
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"LVCMOS18", Series7),
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"xc7vx980t": ("ffg1926-1",
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["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
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"LVCMOS18", Series7),
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}
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def __init__(self, device, pins, std):
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cs_n, clk, mosi, miso = pins[:4]
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io = ["spiflash", 0,
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Subsignal("cs_n", Pins(cs_n)),
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Subsignal("mosi", Pins(mosi)),
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Subsignal("miso", Pins(miso), Misc("PULLUP")),
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IOStandard(std),
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]
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if clk:
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io.append(Subsignal("clk", Pins(clk)))
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for i, p in enumerate(pins[4:]):
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io.append(Subsignal("pullup{}".format(i), Pins(p), Misc("PULLUP")))
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XilinxPlatform.__init__(self, device, [io])
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if isinstance(self.toolchain, XilinxVivadoToolchain):
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self.toolchain.bitstream_commands.append(
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]"
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)
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elif isinstance(self.toolchain, XilinxISEToolchain):
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self.toolchain.bitgen_opt += " -g compress"
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@classmethod
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def make(cls, device, errors=False):
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pkg, pins, std, Top = cls.pinouts[device]
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platform = cls("{}-{}".format(device, pkg), pins, std)
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top = Top(platform)
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name = "bscan_spi_{}".format(device)
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dir = "build_{}".format(device)
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try:
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platform.build(top, build_name=name, build_dir=dir)
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except Exception as e:
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print("ERROR: build failed for {}: {}".format(device, e))
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if errors:
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raise
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if __name__ == "__main__":
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import argparse
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import multiprocessing
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p = argparse.ArgumentParser(description="build bscan_spi bitstreams "
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"for openocd jtagspi flash driver")
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p.add_argument("device", nargs="*",
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default=sorted(list(XilinxBscanSpi.pinouts)),
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help="build for these devices (default: %(default)s)")
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p.add_argument("-p", "--parallel", default=1, type=int,
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help="number of parallel builds (default: %(default)s)")
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args = p.parse_args()
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pool = multiprocessing.Pool(args.parallel)
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pool.map(XilinxBscanSpi.make, args.device, chunksize=1)
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@ -4802,6 +4802,49 @@ flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
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@c "cfi part_id" disabled
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@end deffn
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@deffn {Flash Driver} jtagspi
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@cindex Generic JTAG2SPI driver
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@cindex SPI
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@cindex jtagspi
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@cindex bscan_spi
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Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
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SPI flash connected to them. To access this flash from the host, the device
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is first programmed with a special proxy bitstream that
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exposes the SPI flash on the device's JTAG interface. The flash can then be
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accessed through JTAG.
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Since signaling between JTAG and SPI is compatible, all that is required for
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a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
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the flash chip select when the JTAG state machine is in SHIFT-DR. Such
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a bitstream for several Xilinx FPGAs can be found in
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@file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires migen
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(@url{http://github.com/m-labs/migen}) and a Xilinx toolchain to build.
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This flash bank driver requires a target on a JTAG tap and will access that
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tap directly. Since no support from the target is needed, the target can be a
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"testee" dummy. Since the target does not expose the flash memory
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mapping, target commands that would otherwise be expected to access the flash
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will not work. These include all @command{*_image} and
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@command{$target_name m*} commands as well as @command{program}. Equivalent
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functionality is available through the @command{flash write_bank},
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@command{flash read_bank}, and @command{flash verify_bank} commands.
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@itemize
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@item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
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For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
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@var{USER1} instruction.
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@item @var{dr_length} ... is the length of the DR register. This will be 1 for
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@file{xilinx_bscan_spi.py} bitstreams and most other cases.
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@end itemize
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@example
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target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
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set _XILINX_USER1 0x02
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set _DR_LENGTH 1
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flash bank $_FLASHNAME spi 0x0 0 0 0 $_TARGETNAME $_XILINX_USER1 $_DR_LENGTH
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@end example
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@end deffn
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@deffn {Flash Driver} lpcspifi
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@cindex NXP SPI Flash Interface
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||||
@cindex SPIFI
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ NOR_DRIVERS = \
|
|||
efm32.c \
|
||||
em357.c \
|
||||
faux.c \
|
||||
jtagspi.c \
|
||||
lpc2000.c \
|
||||
lpc288x.c \
|
||||
lpc2900.c \
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@ extern struct flash_driver nrf51_flash;
|
|||
extern struct flash_driver mrvlqspi_flash;
|
||||
extern struct flash_driver psoc4_flash;
|
||||
extern struct flash_driver sim3x_flash;
|
||||
extern struct flash_driver jtagspi_flash;
|
||||
|
||||
/**
|
||||
* The list of built-in flash drivers.
|
||||
|
|
@ -102,6 +103,7 @@ static struct flash_driver *flash_drivers[] = {
|
|||
&mrvlqspi_flash,
|
||||
&psoc4_flash,
|
||||
&sim3x_flash,
|
||||
&jtagspi_flash,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,411 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2015 Robert Jordens <jordens@gmail.com> *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
***************************************************************************/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include "imp.h"
|
||||
#include <jtag/jtag.h>
|
||||
#include <flash/nor/spi.h>
|
||||
#include <helper/time_support.h>
|
||||
|
||||
#define JTAGSPI_MAX_TIMEOUT 3000
|
||||
|
||||
|
||||
struct jtagspi_flash_bank {
|
||||
struct jtag_tap *tap;
|
||||
const struct flash_device *dev;
|
||||
int probed;
|
||||
uint32_t ir;
|
||||
uint32_t dr_len;
|
||||
};
|
||||
|
||||
FLASH_BANK_COMMAND_HANDLER(jtagspi_flash_bank_command)
|
||||
{
|
||||
struct jtagspi_flash_bank *info;
|
||||
|
||||
if (CMD_ARGC < 8)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
|
||||
info = malloc(sizeof(struct jtagspi_flash_bank));
|
||||
if (info == NULL) {
|
||||
LOG_ERROR("no memory for flash bank info");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
bank->driver_priv = info;
|
||||
|
||||
info->tap = NULL;
|
||||
info->probed = 0;
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], info->ir);
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], info->dr_len);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static void jtagspi_set_ir(struct flash_bank *bank)
|
||||
{
|
||||
struct jtagspi_flash_bank *info = bank->driver_priv;
|
||||
struct scan_field field;
|
||||
uint8_t buf[4];
|
||||
|
||||
if (buf_get_u32(info->tap->cur_instr, 0, info->tap->ir_length) == info->ir)
|
||||
return;
|
||||
|
||||
LOG_DEBUG("loading jtagspi ir");
|
||||
buf_set_u32(buf, 0, info->tap->ir_length, info->ir);
|
||||
field.num_bits = info->tap->ir_length;
|
||||
field.out_value = buf;
|
||||
field.in_value = NULL;
|
||||
jtag_add_ir_scan(info->tap, &field, TAP_IDLE);
|
||||
}
|
||||
|
||||
static void flip_u8(uint8_t *in, uint8_t *out, int len)
|
||||
{
|
||||
for (int i = 0; i < len; i++)
|
||||
out[i] = flip_u32(in[i], 8);
|
||||
}
|
||||
|
||||
static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd,
|
||||
uint32_t *addr, uint8_t *data, int len)
|
||||
{
|
||||
struct jtagspi_flash_bank *info = bank->driver_priv;
|
||||
struct scan_field fields[3];
|
||||
uint8_t cmd_buf[4];
|
||||
uint8_t *data_buf;
|
||||
int is_read, lenb, n;
|
||||
|
||||
/* LOG_DEBUG("cmd=0x%02x len=%i", cmd, len); */
|
||||
|
||||
n = 0;
|
||||
fields[n].num_bits = 8;
|
||||
cmd_buf[0] = cmd;
|
||||
if (addr) {
|
||||
h_u24_to_be(cmd_buf + 1, *addr);
|
||||
fields[n].num_bits += 24;
|
||||
}
|
||||
flip_u8(cmd_buf, cmd_buf, 4);
|
||||
fields[n].out_value = cmd_buf;
|
||||
fields[n].in_value = NULL;
|
||||
n++;
|
||||
|
||||
is_read = (len < 0);
|
||||
if (is_read)
|
||||
len = -len;
|
||||
lenb = DIV_ROUND_UP(len, 8);
|
||||
data_buf = malloc(lenb);
|
||||
if (lenb > 0) {
|
||||
if (data_buf == NULL) {
|
||||
LOG_ERROR("no memory for spi buffer");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
if (is_read) {
|
||||
fields[n].num_bits = info->dr_len;
|
||||
fields[n].out_value = NULL;
|
||||
fields[n].in_value = NULL;
|
||||
n++;
|
||||
fields[n].out_value = NULL;
|
||||
fields[n].in_value = data_buf;
|
||||
} else {
|
||||
flip_u8(data, data_buf, lenb);
|
||||
fields[n].out_value = data_buf;
|
||||
fields[n].in_value = NULL;
|
||||
}
|
||||
fields[n].num_bits = len;
|
||||
n++;
|
||||
}
|
||||
|
||||
jtagspi_set_ir(bank);
|
||||
jtag_add_dr_scan(info->tap, n, fields, TAP_IDLE);
|
||||
jtag_execute_queue();
|
||||
|
||||
if (is_read)
|
||||
flip_u8(data_buf, data, lenb);
|
||||
free(data_buf);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int jtagspi_probe(struct flash_bank *bank)
|
||||
{
|
||||
struct jtagspi_flash_bank *info = bank->driver_priv;
|
||||
struct flash_sector *sectors;
|
||||
uint8_t in_buf[3];
|
||||
uint32_t id;
|
||||
|
||||
if (info->probed)
|
||||
free(bank->sectors);
|
||||
info->probed = 0;
|
||||
|
||||
if (bank->target->tap == NULL) {
|
||||
LOG_ERROR("Target has no JTAG tap");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
info->tap = bank->target->tap;
|
||||
|
||||
jtagspi_cmd(bank, SPIFLASH_READ_ID, NULL, in_buf, -24);
|
||||
/* the table in spi.c has the manufacturer byte (first) as the lsb */
|
||||
id = le_to_h_u24(in_buf);
|
||||
|
||||
info->dev = NULL;
|
||||
for (const struct flash_device *p = flash_devices; p->name ; p++)
|
||||
if (p->device_id == id) {
|
||||
info->dev = p;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!(info->dev)) {
|
||||
LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
|
||||
info->dev->name, info->dev->device_id);
|
||||
|
||||
/* Set correct size value */
|
||||
bank->size = info->dev->size_in_bytes;
|
||||
|
||||
/* create and fill sectors array */
|
||||
bank->num_sectors =
|
||||
info->dev->size_in_bytes / info->dev->sectorsize;
|
||||
sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
|
||||
if (sectors == NULL) {
|
||||
LOG_ERROR("not enough memory");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
for (int sector = 0; sector < bank->num_sectors; sector++) {
|
||||
sectors[sector].offset = sector * info->dev->sectorsize;
|
||||
sectors[sector].size = info->dev->sectorsize;
|
||||
sectors[sector].is_erased = -1;
|
||||
sectors[sector].is_protected = 0;
|
||||
}
|
||||
|
||||
bank->sectors = sectors;
|
||||
info->probed = 1;
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static void jtagspi_read_status(struct flash_bank *bank, uint32_t *status)
|
||||
{
|
||||
uint8_t buf;
|
||||
jtagspi_cmd(bank, SPIFLASH_READ_STATUS, NULL, &buf, -8);
|
||||
*status = buf;
|
||||
/* LOG_DEBUG("status=0x%08" PRIx32, *status); */
|
||||
}
|
||||
|
||||
static int jtagspi_wait(struct flash_bank *bank, int timeout_ms)
|
||||
{
|
||||
uint32_t status;
|
||||
long long t0 = timeval_ms();
|
||||
long long dt;
|
||||
|
||||
do {
|
||||
dt = timeval_ms() - t0;
|
||||
jtagspi_read_status(bank, &status);
|
||||
if ((status & SPIFLASH_BSY_BIT) == 0) {
|
||||
LOG_DEBUG("waited %lld ms", dt);
|
||||
return ERROR_OK;
|
||||
}
|
||||
alive_sleep(1);
|
||||
} while (dt <= timeout_ms);
|
||||
|
||||
LOG_ERROR("timeout, device still busy");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
static int jtagspi_write_enable(struct flash_bank *bank)
|
||||
{
|
||||
uint32_t status;
|
||||
|
||||
jtagspi_cmd(bank, SPIFLASH_WRITE_ENABLE, NULL, NULL, 0);
|
||||
jtagspi_read_status(bank, &status);
|
||||
if ((status & SPIFLASH_WE_BIT) == 0) {
|
||||
LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int jtagspi_bulk_erase(struct flash_bank *bank)
|
||||
{
|
||||
struct jtagspi_flash_bank *info = bank->driver_priv;
|
||||
int retval;
|
||||
long long t0 = timeval_ms();
|
||||
|
||||
retval = jtagspi_write_enable(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
jtagspi_cmd(bank, info->dev->chip_erase_cmd, NULL, NULL, 0);
|
||||
retval = jtagspi_wait(bank, bank->num_sectors*JTAGSPI_MAX_TIMEOUT);
|
||||
LOG_INFO("took %lld ms", timeval_ms() - t0);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int jtagspi_sector_erase(struct flash_bank *bank, int sector)
|
||||
{
|
||||
struct jtagspi_flash_bank *info = bank->driver_priv;
|
||||
int retval;
|
||||
long long t0 = timeval_ms();
|
||||
|
||||
retval = jtagspi_write_enable(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
jtagspi_cmd(bank, info->dev->erase_cmd, &bank->sectors[sector].offset, NULL, 0);
|
||||
retval = jtagspi_wait(bank, JTAGSPI_MAX_TIMEOUT);
|
||||
LOG_INFO("sector %d took %lld ms", sector, timeval_ms() - t0);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int jtagspi_erase(struct flash_bank *bank, int first, int last)
|
||||
{
|
||||
int sector;
|
||||
struct jtagspi_flash_bank *info = bank->driver_priv;
|
||||
int retval;
|
||||
|
||||
LOG_DEBUG("erase from sector %d to sector %d", first, last);
|
||||
|
||||
if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
|
||||
LOG_ERROR("Flash sector invalid");
|
||||
return ERROR_FLASH_SECTOR_INVALID;
|
||||
}
|
||||
|
||||
if (!(info->probed)) {
|
||||
LOG_ERROR("Flash bank not probed");
|
||||
return ERROR_FLASH_BANK_NOT_PROBED;
|
||||
}
|
||||
|
||||
for (sector = first; sector <= last; sector++) {
|
||||
if (bank->sectors[sector].is_protected) {
|
||||
LOG_ERROR("Flash sector %d protected", sector);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
if (first == 0 && last == (bank->num_sectors - 1)
|
||||
&& info->dev->chip_erase_cmd != info->dev->erase_cmd) {
|
||||
LOG_DEBUG("Trying bulk erase.");
|
||||
retval = jtagspi_bulk_erase(bank);
|
||||
if (retval == ERROR_OK)
|
||||
return retval;
|
||||
else
|
||||
LOG_WARNING("Bulk flash erase failed. Falling back to sector erase.");
|
||||
}
|
||||
|
||||
for (sector = first; sector <= last; sector++) {
|
||||
retval = jtagspi_sector_erase(bank, sector);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("Sector erase failed.");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int jtagspi_protect(struct flash_bank *bank, int set, int first, int last)
|
||||
{
|
||||
int sector;
|
||||
|
||||
if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
|
||||
LOG_ERROR("Flash sector invalid");
|
||||
return ERROR_FLASH_SECTOR_INVALID;
|
||||
}
|
||||
|
||||
for (sector = first; sector <= last; sector++)
|
||||
bank->sectors[sector].is_protected = set;
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int jtagspi_protect_check(struct flash_bank *bank)
|
||||
{
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int jtagspi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
|
||||
{
|
||||
struct jtagspi_flash_bank *info = bank->driver_priv;
|
||||
|
||||
if (!(info->probed)) {
|
||||
LOG_ERROR("Flash bank not yet probed.");
|
||||
return ERROR_FLASH_BANK_NOT_PROBED;
|
||||
}
|
||||
|
||||
jtagspi_cmd(bank, SPIFLASH_READ, &offset, buffer, -count*8);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int jtagspi_page_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
|
||||
{
|
||||
int retval;
|
||||
|
||||
retval = jtagspi_write_enable(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
jtagspi_cmd(bank, SPIFLASH_PAGE_PROGRAM, &offset, (uint8_t *) buffer, count*8);
|
||||
return jtagspi_wait(bank, JTAGSPI_MAX_TIMEOUT);
|
||||
}
|
||||
|
||||
static int jtagspi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
|
||||
{
|
||||
struct jtagspi_flash_bank *info = bank->driver_priv;
|
||||
int retval;
|
||||
uint32_t n;
|
||||
|
||||
if (!(info->probed)) {
|
||||
LOG_ERROR("Flash bank not yet probed.");
|
||||
return ERROR_FLASH_BANK_NOT_PROBED;
|
||||
}
|
||||
|
||||
for (n = 0; n < count; n += info->dev->pagesize) {
|
||||
retval = jtagspi_page_write(bank, buffer + n, offset + n,
|
||||
MIN(count - n, info->dev->pagesize));
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("page write error");
|
||||
return retval;
|
||||
}
|
||||
LOG_DEBUG("wrote page at 0x%08" PRIx32, offset + n);
|
||||
}
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int jtagspi_info(struct flash_bank *bank, char *buf, int buf_size)
|
||||
{
|
||||
struct jtagspi_flash_bank *info = bank->driver_priv;
|
||||
|
||||
if (!(info->probed)) {
|
||||
snprintf(buf, buf_size, "\nJTAGSPI flash bank not probed yet\n");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
snprintf(buf, buf_size, "\nSPIFI flash information:\n"
|
||||
" Device \'%s\' (ID 0x%08" PRIx32 ")\n",
|
||||
info->dev->name, info->dev->device_id);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
struct flash_driver jtagspi_flash = {
|
||||
.name = "jtagspi",
|
||||
.flash_bank_command = jtagspi_flash_bank_command,
|
||||
.erase = jtagspi_erase,
|
||||
.protect = jtagspi_protect,
|
||||
.write = jtagspi_write,
|
||||
.read = jtagspi_read,
|
||||
.probe = jtagspi_probe,
|
||||
.auto_probe = jtagspi_probe,
|
||||
.erase_check = default_flash_blank_check,
|
||||
.protect_check = jtagspi_protect_check,
|
||||
.info = jtagspi_info
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
set _USER1 0x02
|
||||
|
||||
if { [info exists JTAGSPI_IR] } {
|
||||
set _JTAGSPI_IR $JTAGSPI_IR
|
||||
} else {
|
||||
set _JTAGSPI_IR $_USER1
|
||||
}
|
||||
|
||||
if { [info exists DR_LENGTH] } {
|
||||
set _DR_LENGTH $DR_LENGTH
|
||||
} else {
|
||||
set _DR_LENGTH 1
|
||||
}
|
||||
|
||||
if { [info exists TARGETNAME] } {
|
||||
set _TARGETNAME $TARGETNAME
|
||||
} else {
|
||||
set _TARGETNAME $_CHIPNAME.proxy
|
||||
}
|
||||
|
||||
if { [info exists FLASHNAME] } {
|
||||
set _FLASHNAME $FLASHNAME
|
||||
} else {
|
||||
set _FLASHNAME $_CHIPNAME.spi
|
||||
}
|
||||
|
||||
target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
|
||||
flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR $_DR_LENGTH
|
||||
|
||||
proc jtagspi_init {chain_id proxy_bit} {
|
||||
# load proxy bitstream $proxy_bit and probe spi flash
|
||||
global _FLASHNAME
|
||||
pld load $chain_id $proxy_bit
|
||||
reset halt
|
||||
flash probe $_FLASHNAME
|
||||
}
|
||||
|
||||
proc jtagspi_program {bin addr} {
|
||||
# write and verify binary file $bin at offset $addr
|
||||
global _FLASHNAME
|
||||
flash write_image erase $bin $addr
|
||||
flash verify_bank $_FLASHNAME $bin $addr
|
||||
}
|
||||
Loading…
Reference in New Issue