interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

tcl: target: am437x: pass coreid 

This commit is only for the sake of completeness as
default coreid is zero. In any case, coreids 1-4 are
used for the different PRU cores inside the SoC.

Change-Id: I775f2f444b1a908ffaf7bdbc43bcc966f19668c4
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2621
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Felipe Balbi 2015-03-18 16:01:00 -05:00 committed by Paul Fertser
parent beb61c6999
commit 1d8c36e16a
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tcl/target/am437x.cfg
View File

@ -486,7 +486,7 @@ jtag configure $JRC_NAME -event post-reset "runtest 100"
#
# Cortex A9 target
#
target create $_TARGETNAME cortex_a -chain-position $DEBUGSS_NAME -dbgbase 0x80000000
target create $_TARGETNAME cortex_a -chain-position $DEBUGSS_NAME -coreid 0 -dbgbase 0x80000000
# SRAM: 256K at 0x4030.0000