stm8 : new target
New STM8 target based mostly on mips4k. Target communication through STLINK/SWIM. No flash driver yet but it is still possible to program flash through load_image command. The usual target debug methods are implemented. Change-Id: I7216f231d3ac7c70cae20f1cd8463c2ed864a329 Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com> Reviewed-on: http://openocd.zylin.com/3953 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Ake Rehnman
Paul Fertser
parent
6090a5b158
commit
020cb12077
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@ -1,6 +1,6 @@
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.PHONY: arm clean-arm
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all: arm
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all: arm stm8
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common_dirs = \
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checksum \
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@ -32,3 +32,6 @@ clean: clean-arm
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for d in $(common_dirs); do \
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$(MAKE) -C $$d clean; \
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done
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stm8:
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$(MAKE) -C erase_check stm8
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@ -6,6 +6,12 @@ ARM_OBJCOPY ?= $(ARM_CROSS_COMPILE)objcopy
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ARM_AFLAGS = -EL
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STM8_CROSS_COMPILE ?= stm8-
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STM8_AS ?= $(STM8_CROSS_COMPILE)as
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STM8_OBJCOPY ?= $(STM8_CROSS_COMPILE)objcopy
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STM8_AFLAGS =
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arm: armv4_5_erase_check.inc armv7m_erase_check.inc armv7m_0_erase_check.inc
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armv4_5_%.elf: armv4_5_%.s
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@ -26,5 +32,16 @@ armv7m_%.bin: armv7m_%.elf
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armv7m_%.inc: armv7m_%.bin
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$(BIN2C) < $< > $@
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stm8: stm8_erase_check.inc
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stm8_%.elf: stm8_%.s
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$(STM8_AS) $(STM8_AFLAGS) $< -o $@
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stm8_%.bin: stm8_%.elf
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$(STM8_OBJCOPY) -Obinary $< $@
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stm8_%.inc: stm8_%.bin
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$(BIN2C) < $< > $@
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clean:
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-rm -f *.elf *.bin *.inc
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@ -0,0 +1,5 @@
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/* Autogenerated with ../../../src/helper/bin2char.sh */
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0x00,0x80,0x00,0x00,0x80,0x00,0x96,0xcf,0x00,0x22,0x1e,0x01,0x16,0x04,0xa6,0xff,
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0x90,0x5d,0x26,0x04,0x0d,0x03,0x27,0x17,0x90,0x5d,0x26,0x02,0x0a,0x03,0x90,0x5a,
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0x92,0xbc,0x00,0x00,0xa1,0xff,0x26,0x07,0x5c,0x26,0xe5,0x0c,0x00,0x20,0xe1,0x1f,
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0x01,0x17,0x04,0x8b,
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@ -0,0 +1,69 @@
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/*
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Copyright (C) 2017 Ake Rehnman
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ake.rehnman(at)gmail.com
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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;;
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;; erase check memory code
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;;
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.org 0x0
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;; start address
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start_addr: .byte 0x00
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.word 0x8000
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;; byte count
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byte_cnt: .byte 0x00
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.word 0x8000
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;
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; SP must point to start_addr on entry
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; first relocate start_addr to the location
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; we are running at
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start:
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ldw X,SP
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ldw .cont+2,X
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ldw X,(start_addr+1,SP) ;start addr
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ldw Y,(byte_cnt+1,SP) ;count
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ld A,#0xff
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;
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; if count == 0 return
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.L1:
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tnzw Y
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jrne .decrcnt ;continue if low word != 0
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tnz (byte_cnt,SP) ;high byte
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jreq .exit ;goto exit
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;
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; decrement count (byte_cnt)
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.decrcnt:
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tnzw Y ;low word count
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jrne .decr1
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dec (byte_cnt,SP) ;high byte
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.decr1:
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decw Y; decr low word
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;
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; first check if [start_addr] is 0xff
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.cont:
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ldf A, [start_addr.e]
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cp A,#0xff
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jrne .exit ;exit if not 0xff
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;
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; increment start_addr (addr)
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incw X
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jrne .L1
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inc (start_addr,SP) ;increment high byte
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jra .L1
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;
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.exit:
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ldw (start_addr+1,SP),X ;start addr
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ldw (byte_cnt+1,SP),Y ;count
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break
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@ -19,6 +19,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
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$(AVR32_SRC) \
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$(MIPS32_SRC) \
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$(NDS32_SRC) \
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$(STM8_SRC) \
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$(INTEL_IA32_SRC) \
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%D%/avrt.c \
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%D%/dsp563xx.c \
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@ -124,6 +125,9 @@ NDS32_SRC = \
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%D%/nds32_v3m.c \
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%D%/nds32_aice.c
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STM8_SRC = \
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%D%/stm8.c
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INTEL_IA32_SRC = \
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%D%/quark_x10xx.c \
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%D%/quark_d20xx.c \
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@ -205,6 +209,7 @@ INTEL_IA32_SRC = \
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%D%/nds32_v3.h \
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%D%/nds32_v3m.h \
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%D%/nds32_aice.h \
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%D%/stm8.h \
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%D%/lakemont.h \
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%D%/x86_32_common.h \
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%D%/arm_cti.h
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,75 @@
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/*
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OpenOCD STM8 target driver
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Copyright (C) 2017 Ake Rehnman
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ake.rehnman(at)gmail.com
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef OPENOCD_TARGET_STM8_H
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#define OPENOCD_TARGET_STM8_H
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struct target;
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#define STM8_COMMON_MAGIC 0x53544D38
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#define STM8_NUM_CORE_REGS 6
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struct stm8_common {
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uint32_t common_magic;
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void *arch_info;
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struct reg_cache *core_cache;
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uint32_t core_regs[STM8_NUM_CORE_REGS];
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/* working area for fastdata access */
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struct working_area *fast_data_area;
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bool swim_configured;
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bool bp_scanned;
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uint8_t num_hw_bpoints;
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uint8_t num_hw_bpoints_avail;
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struct stm8_comparator *hw_break_list;
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uint32_t blocksize;
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uint32_t flashstart;
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uint32_t flashend;
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uint32_t eepromstart;
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uint32_t eepromend;
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uint32_t optionstart;
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uint32_t optionend;
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bool enable_step_irq;
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bool enable_stm8l;
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uint32_t flash_cr2;
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uint32_t flash_ncr2;
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uint32_t flash_iapsr;
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uint32_t flash_dukr;
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uint32_t flash_pukr;
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/* cc value used for interrupt flags restore */
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uint32_t cc;
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bool cc_valid;
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/* register cache to processor synchronization */
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int (*read_core_reg)(struct target *target, unsigned int num);
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int (*write_core_reg)(struct target *target, unsigned int num);
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};
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static inline struct stm8_common *
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target_to_stm8(struct target *target)
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{
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return target->arch_info;
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}
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const struct command_registration stm8_command_handlers[];
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#endif /* OPENOCD_TARGET_STM8_H */
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@ -105,6 +105,7 @@ extern struct target_type nds32_v3m_target;
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extern struct target_type or1k_target;
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extern struct target_type quark_x10xx_target;
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extern struct target_type quark_d20xx_target;
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extern struct target_type stm8_target;
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static struct target_type *target_types[] = {
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&arm7tdmi_target,
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@ -136,6 +137,7 @@ static struct target_type *target_types[] = {
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&or1k_target,
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&quark_x10xx_target,
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&quark_d20xx_target,
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&stm8_target,
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#if BUILD_TARGET64
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&aarch64_target,
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#endif
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@ -0,0 +1,87 @@
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# script for stm8l family
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#
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# stm8 devices support SWIM transports only.
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#
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transport select stlink_swim
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm8l
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 1kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x400
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}
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if { [info exists FLASHSTART] } {
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set _FLASHSTART $FLASHSTART
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} else {
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set _FLASHSTART 0x8000
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}
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if { [info exists FLASHEND] } {
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set _FLASHEND $FLASHEND
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} else {
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set _FLASHEND 0xffff
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}
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if { [info exists EEPROMSTART] } {
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set _EEPROMSTART $EEPROMSTART
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} else {
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set _EEPROMSTART 0x4000
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}
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if { [info exists EEPROMEND] } {
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set _EEPROMEND $EEPROMEND
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} else {
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set _EEPROMEND 0x43ff
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}
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if { [info exists OPTIONSTART] } {
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set _OPTIONSTART $OPTIONSTART
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} else {
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set _OPTIONSTART 0x4800
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}
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if { [info exists OPTIONEND] } {
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set _OPTIONEND $OPTIONEND
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} else {
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set _OPTIONEND 0x487f
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}
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if { [info exists BLOCKSIZE] } {
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set _BLOCKSIZE $BLOCKSIZE
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} else {
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set _BLOCKSIZE 0x80
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}
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hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu
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$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1
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$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND
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$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE
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# Uncomment this line to enable interrupts while instruction step
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#$_TARGETNAME configure -enable_step_irq
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# Set stm8l type
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$_TARGETNAME configure -enable_stm8l
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# The khz rate does not apply here, only slow <0> and fast <1>
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adapter_khz 1
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reset_config srst_only
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#uncomment this line to connect under reset
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#reset_config srst_nogate connect_assert_srst
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@ -0,0 +1,84 @@
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# script for stm8s family
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#
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# stm8 devices support SWIM transports only.
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#
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transport select stlink_swim
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm8s
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 1kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x400
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}
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if { [info exists FLASHSTART] } {
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set _FLASHSTART $FLASHSTART
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} else {
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set _FLASHSTART 0x8000
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}
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if { [info exists FLASHEND] } {
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set _FLASHEND $FLASHEND
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} else {
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set _FLASHEND 0xffff
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}
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if { [info exists EEPROMSTART] } {
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set _EEPROMSTART $EEPROMSTART
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} else {
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set _EEPROMSTART 0x4000
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}
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if { [info exists EEPROMEND] } {
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set _EEPROMEND $EEPROMEND
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} else {
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set _EEPROMEND 0x43ff
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}
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if { [info exists OPTIONSTART] } {
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set _OPTIONSTART $OPTIONSTART
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} else {
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set _OPTIONSTART 0x4800
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}
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if { [info exists OPTIONEND] } {
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set _OPTIONEND $OPTIONEND
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} else {
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set _OPTIONEND 0x487f
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}
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if { [info exists BLOCKSIZE] } {
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set _BLOCKSIZE $BLOCKSIZE
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} else {
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set _BLOCKSIZE 0x80
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}
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hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu
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$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1
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$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND
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$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE
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# Uncomment this line to enable interrupts while instruction step
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#$_TARGETNAME configure -enable_step_irq
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# The khz rate does not apply here, only slow <0> and fast <1>
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adapter_khz 1
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reset_config srst_only
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# uncomment this line to connect under reset
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#reset_config srst_nogate connect_assert_srst
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