tcl: am437x: add reset-init event handler
this event handler will configure and lock PLLs and configure DDR so platform is placed in usable state. Change-Id: Idd02f4c9789181d69578f8606ac3576ea1dd8a0b Tested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-on: http://openocd.zylin.com/2616 Tested-by: jenkins Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Felipe Balbi
Paul Fertser
parent
d85a0a6a0c
commit
5df0dfb7f4
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@ -508,5 +508,487 @@ proc disable_watchdog { } {
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}
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}
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proc ceil { x y } {
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return [ expr ($x + $y - 1) / $y ]
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}
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proc device_type { } {
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global CONTROL_STATUS
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set tmp [ mrw $CONTROL_STATUS ]
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set tmp [ expr $tmp & 0x700 ]
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set tmp [ expr $tmp >> 8 ]
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return $tmp
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}
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proc get_input_clock_frequency { } {
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global CONTROL_STATUS
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if { [ device_type ] != 3 } {
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error "Unknown device type\n"
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return -1
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}
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set freq [ mrw $CONTROL_STATUS ]
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set freq [ expr $freq & 0x00c00000 ]
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set freq [ expr $freq >> 22 ]
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switch $freq {
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0 {
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set CLKIN 19200000
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}
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1 {
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set CLKIN 24000000
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}
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2 {
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set CLKIN 25000000
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}
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3 {
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set CLKIN 26000000
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}
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}
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return $CLKIN
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}
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proc mpu_pll_config { CLKIN N M M2 } {
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global CM_CLKMODE_DPLL_MPU
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global CM_CLKSEL_DPLL_MPU
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global CM_DIV_M2_DPLL_MPU
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global CM_IDLEST_DPLL_MPU
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set clksel [ mrw $CM_CLKSEL_DPLL_MPU ]
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set div_m2 [ mrw $CM_DIV_M2_DPLL_MPU ]
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mww $CM_CLKMODE_DPLL_MPU 0x4
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while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { }
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set clksel [ expr $clksel & (~0x7ffff) ]
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set clksel [ expr $clksel | ($M << 0x8) | $N ]
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mww $CM_CLKSEL_DPLL_MPU $clksel
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set div_m2 [ expr $div_m2 & (~0x1f) ]
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set div_m2 [ expr $div_m2 | $M2 ]
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mww $CM_DIV_M2_DPLL_MPU $div_m2
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mww $CM_CLKMODE_DPLL_MPU 0x7
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while { [ mrw $CM_IDLEST_DPLL_MPU ] != 1 } { }
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echo "MPU DPLL locked"
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}
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proc core_pll_config { CLKIN N M M4 M5 M6 } {
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global CM_CLKMODE_DPLL_CORE
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global CM_CLKSEL_DPLL_CORE
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global CM_DIV_M4_DPLL_CORE
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global CM_DIV_M5_DPLL_CORE
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global CM_DIV_M6_DPLL_CORE
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global CM_IDLEST_DPLL_CORE
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set clksel [ mrw $CM_CLKSEL_DPLL_CORE ]
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mww $CM_CLKMODE_DPLL_CORE 0x4
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while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { }
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set clksel [ expr $clksel & (~0x7ffff) ]
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set clksel [ expr $clksel | ($M << 0x8) | $N ]
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mww $CM_CLKSEL_DPLL_CORE $clksel
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mww $CM_DIV_M4_DPLL_CORE $M4
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mww $CM_DIV_M5_DPLL_CORE $M5
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mww $CM_DIV_M6_DPLL_CORE $M6
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mww $CM_CLKMODE_DPLL_CORE 0x7
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while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x01) } { }
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echo "CORE DPLL locked"
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}
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proc per_pll_config { CLKIN N M M2 } {
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global CM_CLKMODE_DPLL_PER
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global CM_CLKSEL_DPLL_PER
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global CM_DIV_M2_DPLL_PER
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global CM_IDLEST_DPLL_PER
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set x [ expr $M * $CLKIN / 1000000 ]
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set y [ expr ($N + 1) * 250 ]
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set sd [ ceil $x $y ]
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set clksel [ mrw $CM_CLKSEL_DPLL_PER ]
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set div_m2 [ mrw $CM_DIV_M2_DPLL_PER ]
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mww $CM_CLKMODE_DPLL_PER 0x4
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while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { }
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set clksel [ expr $clksel & (~0xff0fffff) ]
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set clksel [ expr $clksel | ($M << 0x8) | $N ]
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set clksel [ expr $clksel | ($sd << 24) ]
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mww $CM_CLKSEL_DPLL_PER $clksel
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set div_m2 [ expr 0xffffff80 | $M2 ]
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mww $CM_CLKMODE_DPLL_PER 0x7
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while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { }
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echo "PER DPLL locked"
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}
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proc ddr_pll_config { CLKIN N M M2 M4 } {
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global CM_CLKMODE_DPLL_DDR
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global CM_CLKSEL_DPLL_DDR
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global CM_DIV_M2_DPLL_DDR
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global CM_DIV_M4_DPLL_DDR
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global CM_IDLEST_DPLL_DDR
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set clksel [ mrw $CM_CLKSEL_DPLL_DDR ]
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set div_m2 [ mrw $CM_DIV_M2_DPLL_DDR ]
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mww $CM_CLKMODE_DPLL_DDR 0x4
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while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { }
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set clksel [ expr $clksel & (~0x7ffff) ]
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set clksel [ expr $clksel | ($M << 8) | $N ]
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mww $CM_CLKSEL_DPLL_DDR $clksel
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set div_m2 [ expr ($div_m2 & 0xffffffe0) | $M2 ]
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mww $CM_DIV_M2_DPLL_DDR $div_m2
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mww $CM_DIV_M4_DPLL_DDR $M4
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mww $CM_CLKMODE_DPLL_DDR 0x7
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while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x01) } { }
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echo "DDR DPLL Locked"
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}
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proc config_opp100 { } {
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set CLKIN [ get_input_clock_frequency ]
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if { $CLKIN == -1 } {
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return -1
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}
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switch $CLKIN {
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24000000 {
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mpu_pll_config $CLKIN 0 25 1
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core_pll_config $CLKIN 2 125 10 8 4
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per_pll_config $CLKIN 9 400 5
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ddr_pll_config $CLKIN 2 50 1 2
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}
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25000000 {
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mpu_pll_config $CLKIN 0 24 1
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core_pll_config $CLKIN 0 40 10 8 4
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per_pll_config $CLKIN 9 384 5
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ddr_pll_config $CLKIN 0 16 1 2
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}
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26000000 {
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mpu_pll_config $CLKIN 12 300 1
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core_pll_config $CLKIN 12 500 10 8 4
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per_pll_config $CLKIN 12 480 5
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ddr_pll_config $CLKIN 12 200 1 2
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}
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19200000 {
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mpu_pll_config $CLKIN 3 125 1
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core_pll_config $CLKIN 11 625 10 8 4
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per_pll_config $CLKIN 7 400 5
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ddr_pll_config $CLKIN 2 125 1 2
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}
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}
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}
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proc emif_prcm_clk_enable { } {
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global CM_PER_EMIF_FW_CLKCTRL
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global CM_PER_EMIF_CLKCTRL
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mww $CM_PER_EMIF_FW_CLKCTRL 0x02
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mww $CM_PER_EMIF_CLKCTRL 0x02
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while { [ mrw $CM_PER_EMIF_CLKCTRL ] != 0x02 } { }
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}
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proc vtp_enable { } {
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global VTP_CTRL_REG
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set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x40 ]
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mww $VTP_CTRL_REG $vtp
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set vtp [ expr [ mrw $VTP_CTRL_REG ] & ~0x01 ]
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mww $VTP_CTRL_REG $vtp
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set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x01 ]
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mww $VTP_CTRL_REG $vtp
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}
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proc config_ddr_ioctrl { } {
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global DDR_ADDRCTRL_IOCTRL
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global DDR_ADDRCTRL_WD0_IOCTRL
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global DDR_ADDRCTRL_WD1_IOCTRL
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global DDR_CKE_CTRL
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global DDR_DATA0_IOCTRL
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global DDR_DATA1_IOCTRL
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global DDR_DATA2_IOCTRL
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global DDR_DATA3_IOCTRL
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global DDR_IO_CTRL
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mww $DDR_ADDRCTRL_IOCTRL 0x84
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mww $DDR_ADDRCTRL_WD0_IOCTRL 0x00
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mww $DDR_ADDRCTRL_WD1_IOCTRL 0x00
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mww $DDR_DATA0_IOCTRL 0x84
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mww $DDR_DATA1_IOCTRL 0x84
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mww $DDR_DATA2_IOCTRL 0x84
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mww $DDR_DATA3_IOCTRL 0x84
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mww $DDR_IO_CTRL 0x00
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mww $DDR_CKE_CTRL 0x03
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}
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proc config_ddr_phy { } {
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global EMIF_DDR_PHY_CTRL_1
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global EMIF_DDR_PHY_CTRL_1_SHDW
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global EXT_PHY_CTRL_1
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global EXT_PHY_CTRL_1_SHDW
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global EXT_PHY_CTRL_2
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global EXT_PHY_CTRL_2_SHDW
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global EXT_PHY_CTRL_3
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global EXT_PHY_CTRL_3_SHDW
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global EXT_PHY_CTRL_4
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global EXT_PHY_CTRL_4_SHDW
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global EXT_PHY_CTRL_5
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global EXT_PHY_CTRL_5_SHDW
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global EXT_PHY_CTRL_6
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global EXT_PHY_CTRL_6_SHDW
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global EXT_PHY_CTRL_7
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global EXT_PHY_CTRL_7_SHDW
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global EXT_PHY_CTRL_8
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global EXT_PHY_CTRL_8_SHDW
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global EXT_PHY_CTRL_9
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global EXT_PHY_CTRL_9_SHDW
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global EXT_PHY_CTRL_10
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global EXT_PHY_CTRL_10_SHDW
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global EXT_PHY_CTRL_11
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global EXT_PHY_CTRL_11_SHDW
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global EXT_PHY_CTRL_12
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global EXT_PHY_CTRL_12_SHDW
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global EXT_PHY_CTRL_13
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global EXT_PHY_CTRL_13_SHDW
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global EXT_PHY_CTRL_14
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global EXT_PHY_CTRL_14_SHDW
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global EXT_PHY_CTRL_15
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global EXT_PHY_CTRL_15_SHDW
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global EXT_PHY_CTRL_16
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global EXT_PHY_CTRL_16_SHDW
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global EXT_PHY_CTRL_17
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global EXT_PHY_CTRL_17_SHDW
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global EXT_PHY_CTRL_18
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global EXT_PHY_CTRL_18_SHDW
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global EXT_PHY_CTRL_19
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global EXT_PHY_CTRL_19_SHDW
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global EXT_PHY_CTRL_20
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global EXT_PHY_CTRL_20_SHDW
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global EXT_PHY_CTRL_21
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global EXT_PHY_CTRL_21_SHDW
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global EXT_PHY_CTRL_22
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global EXT_PHY_CTRL_22_SHDW
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global EXT_PHY_CTRL_23
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global EXT_PHY_CTRL_23_SHDW
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global EXT_PHY_CTRL_24
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global EXT_PHY_CTRL_24_SHDW
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global EXT_PHY_CTRL_25
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global EXT_PHY_CTRL_25_SHDW
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global EXT_PHY_CTRL_26
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global EXT_PHY_CTRL_26_SHDW
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global EXT_PHY_CTRL_27
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global EXT_PHY_CTRL_27_SHDW
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global EXT_PHY_CTRL_28
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global EXT_PHY_CTRL_28_SHDW
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global EXT_PHY_CTRL_29
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global EXT_PHY_CTRL_29_SHDW
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global EXT_PHY_CTRL_30
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global EXT_PHY_CTRL_30_SHDW
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global EXT_PHY_CTRL_31
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global EXT_PHY_CTRL_31_SHDW
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global EXT_PHY_CTRL_32
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global EXT_PHY_CTRL_32_SHDW
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global EXT_PHY_CTRL_33
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global EXT_PHY_CTRL_33_SHDW
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global EXT_PHY_CTRL_34
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global EXT_PHY_CTRL_34_SHDW
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global EXT_PHY_CTRL_35
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global EXT_PHY_CTRL_35_SHDW
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global EXT_PHY_CTRL_36
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global EXT_PHY_CTRL_36_SHDW
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mww $EMIF_DDR_PHY_CTRL_1 0x8009
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mww $EMIF_DDR_PHY_CTRL_1_SHDW 0x8009
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set slave_ratio 0x80
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set gatelvl_init_ratio 0x20
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set wr_dqs_slave_delay 0x60
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set rd_dqs_slave_delay 0x60
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set dq_offset 0x40
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set gatelvl_init_mode 0x01
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set wr_data_slave_delay 0x80
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set gatelvl_num_dq0 0x0f
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set wrlvl_num_dq0 0x0f
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mww $EXT_PHY_CTRL_1 [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ]
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mww $EXT_PHY_CTRL_1_SHDW [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ]
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mww $EXT_PHY_CTRL_26 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
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mww $EXT_PHY_CTRL_26_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
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mww $EXT_PHY_CTRL_27 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
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mww $EXT_PHY_CTRL_27_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
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mww $EXT_PHY_CTRL_28 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
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mww $EXT_PHY_CTRL_28_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
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mww $EXT_PHY_CTRL_29 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
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mww $EXT_PHY_CTRL_29_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
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mww $EXT_PHY_CTRL_30 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
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mww $EXT_PHY_CTRL_30_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
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mww $EXT_PHY_CTRL_31 0x00
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mww $EXT_PHY_CTRL_31_SHDW 0x00
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mww $EXT_PHY_CTRL_32 0x00
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mww $EXT_PHY_CTRL_32_SHDW 0x00
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mww $EXT_PHY_CTRL_33 0x00
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mww $EXT_PHY_CTRL_33_SHDW 0x00
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mww $EXT_PHY_CTRL_34 0x00
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mww $EXT_PHY_CTRL_34_SHDW 0x00
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mww $EXT_PHY_CTRL_35 0x00
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mww $EXT_PHY_CTRL_35_SHDW 0x00
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mww $EXT_PHY_CTRL_22 0x00
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mww $EXT_PHY_CTRL_22_SHDW 0x00
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mww $EXT_PHY_CTRL_23 [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ]
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mww $EXT_PHY_CTRL_23_SHDW [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ]
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mww $EXT_PHY_CTRL_24 [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay ]
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mww $EXT_PHY_CTRL_24_SHDW [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0 ]
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mww $EXT_PHY_CTRL_25 [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ]
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mww $EXT_PHY_CTRL_25_SHDW [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ]
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mww $EXT_PHY_CTRL_36 [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ]
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mww $EXT_PHY_CTRL_36_SHDW [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ]
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}
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proc config_ddr_timing { } {
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global EMIF_SDRAM_TIM_1
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global EMIF_SDRAM_TIM_2
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global EMIF_SDRAM_TIM_3
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global EMIF_SDRAM_TIM_1_SHDW
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global EMIF_SDRAM_TIM_2_SHDW
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global EMIF_SDRAM_TIM_3_SHDW
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global EMIF_ZQ_CONFIG
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mww $EMIF_SDRAM_TIM_1 0xeaaad4db
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mww $EMIF_SDRAM_TIM_1_SHDW 0xeaaad4db
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mww $EMIF_SDRAM_TIM_2 0x266b7fda
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mww $EMIF_SDRAM_TIM_2_SHDW 0x266b7fda
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mww $EMIF_SDRAM_TIM_3 0x107f8678
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mww $EMIF_SDRAM_TIM_3_SHDW 0x107f8678
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mww $EMIF_ZQ_CONFIG 0x50074be4
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}
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proc config_ddr_pm { } {
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global EMIF_PWR_MGMT_CTRL
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global EMIF_PWR_MGMT_CTRL_SHDW
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global EMIF_DLL_CALIB_CTRL
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global EMIF_DLL_CALIB_CTRL_SHDW
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global EMIF_TEMP_ALERT_CONFIG
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mww $EMIF_PWR_MGMT_CTRL 0x00
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mww $EMIF_PWR_MGMT_CTRL_SHDW 0x00
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mww $EMIF_DLL_CALIB_CTRL 0x00050000
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mww $EMIF_DLL_CALIB_CTRL_SHDW 0x00050000
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mww $EMIF_TEMP_ALERT_CONFIG 0x00
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}
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proc config_ddr_priority { } {
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global EMIF_PRI_COS_MAP
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global EMIF_CONNID_COS_1_MAP
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global EMIF_CONNID_COS_2_MAP
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global EMIF_RD_WR_EXEC_THRSH
|
||||
global COS_CONFIG
|
||||
|
||||
mww $EMIF_PRI_COS_MAP 0x00
|
||||
mww $EMIF_CONNID_COS_1_MAP 0x00
|
||||
mww $EMIF_CONNID_COS_2_MAP 0x0
|
||||
mww $EMIF_RD_WR_EXEC_THRSH 0x0405
|
||||
mww $COS_CONFIG 0x00ffffff
|
||||
}
|
||||
|
||||
proc config_ddr3 { SDRAM_CONFIG } {
|
||||
global CM_DLL_CTRL
|
||||
global EMIF_IODFT_TLGC
|
||||
global EMIF_RDWR_LVL_CTRL
|
||||
global EMIF_RDWR_LVL_RMP_CTRL
|
||||
global EMIF_SDRAM_CONFIG
|
||||
global EMIF_SDRAM_CONFIG_EXT
|
||||
global EMIF_SDRAM_REF_CTRL
|
||||
global EMIF_SDRAM_REF_CTRL_SHDW
|
||||
global EMIF_STATUS
|
||||
global EXT_PHY_CTRL_36
|
||||
global EXT_PHY_CTRL_36_SHDW
|
||||
|
||||
emif_prcm_clk_enable
|
||||
vtp_enable
|
||||
|
||||
set dll [ expr [ mrw $CM_DLL_CTRL ] & ~0x01 ]
|
||||
mww $CM_DLL_CTRL $dll
|
||||
while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { }
|
||||
|
||||
config_ddr_ioctrl
|
||||
|
||||
mww $EMIF_SDRAM_CONFIG_EXT 0xc163
|
||||
mww $EMIF_IODFT_TLGC 0x2011
|
||||
mww $EMIF_IODFT_TLGC 0x2411
|
||||
mww $EMIF_IODFT_TLGC 0x2011
|
||||
mww $EMIF_SDRAM_REF_CTRL 0x80003000
|
||||
|
||||
config_ddr_phy
|
||||
|
||||
mww $EMIF_IODFT_TLGC 0x2011
|
||||
mww $EMIF_IODFT_TLGC 0x2411
|
||||
mww $EMIF_IODFT_TLGC 0x2011
|
||||
|
||||
config_ddr_timing
|
||||
config_ddr_pm
|
||||
config_ddr_priority
|
||||
|
||||
mww $EMIF_SDRAM_REF_CTRL 0x3000
|
||||
mww $EMIF_SDRAM_CONFIG $SDRAM_CONFIG
|
||||
|
||||
mww $EMIF_SDRAM_REF_CTRL 0x0c30
|
||||
mww $EMIF_SDRAM_REF_CTRL_SHDW 0x0c30
|
||||
|
||||
sleep 10
|
||||
|
||||
set tmp [ expr [ mrw $EXT_PHY_CTRL_36 ] | 0x0100 ]
|
||||
mww $EXT_PHY_CTRL_36 $tmp
|
||||
mww $EXT_PHY_CTRL_36_SHDW $tmp
|
||||
|
||||
mww $EMIF_RDWR_LVL_RMP_CTRL 0x80000000
|
||||
mww $EMIF_RDWR_LVL_CTRL 0x80000000
|
||||
|
||||
while { [ mrw $EMIF_RDWR_LVL_CTRL ] & 0x80000000 } { }
|
||||
|
||||
if { [ mrw $EMIF_STATUS ] & 0x70 } {
|
||||
error "DDR3 Hardware Leveling incomplete!!!"
|
||||
}
|
||||
}
|
||||
|
||||
proc init_platform { SDRAM_CONFIG } {
|
||||
config_opp100
|
||||
config_ddr3 $SDRAM_CONFIG
|
||||
|
||||
# now that PLLs are configured, we can run JTAG at full speed
|
||||
adapter_khz 16000
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
|
||||
$_TARGETNAME configure -event reset-init { init_platform 0x61a013b2 }
|
||||
$_TARGETNAME configure -event reset-end { disable_watchdog }
|
||||
|
|
|
|||
Loading…
Reference in New Issue