interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

target: atheros_ar9344: add simple uart0 test 

in some cases we need something to test if uart is actually
properly connected.

Change-Id: I5a16b053164b34bb30ae8370753be12887a85c51
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4194
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Oleksij Rempel 2017-08-06 09:50:05 +02:00 committed by Spencer Oliver
parent ffa745b835
commit 5384d2c209
1 changed files with 23 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
tcl/target/atheros_ar9344.cfg
View File

@ -14,3 +14,26 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
proc test_ar9344_uart0_tx {} {
echo "configuring uart0.."
mww 0xb802000c 0x87
mww 0xb8020000 0x15
mww 0xb8020004 0
mww 0xb802000c 7
mww 0xb8020004 0
echo "send message: hallo world"
mww 0xb8020000 0x68
mww 0xb8020000 0x65
mww 0xb8020000 0x6c
mww 0xb8020000 0x6c
mww 0xb8020000 0x6f
mww 0xb8020000 0x20
mww 0xb8020000 0x77
mww 0xb8020000 0x6f
mww 0xb8020000 0x72
mww 0xb8020000 0x6c
mww 0xb8020000 0x64
mww 0xb8020000 0x0a
}