This patch is picked from the tcl part of OpenOCD-Nuvoton's commit
("flash: supported Nuvoton M4 series. jtag: Used HW reset instead of
auto reset. tcl: added a configuration file for Nuvoton M4 series.") [1]
to support the communication with Nuvoton's Cortex-M4 chips: M541 &
NUC442/472 series.
This patch has been tested with Nuvoton's NuTiny-SDK-NUC472 development
board [2].
The code comes from the commit basically. Jian-Hong Pan tweaked for the
compatibility with current OpenOCD. So, leave the author as Zale Yu.
[1]: https://github.com/OpenNuvoton/OpenOCD-Nuvoton/commit/c2d5b8bfc705
[2]: https://www.nuvoton.com/export/resource-files/UM_NuTiny-SDK-
NUC472_EN_Rev1.02.pdf
Signed-off-by: Zale Yu <cyyu@nuvoton.com>
Signed-off-by: Jian-Hong Pan <chienhung.pan@gmail.com>
Change-Id: I27ac58dd1c98a76e791a4f1117c31060cf5522e8
Reviewed-on: https://review.openocd.org/c/openocd/+/7330
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
rp2040-core0.cfg configuration file was intended for a special adapter
which selects a SWD multidrop target on its own. This means
that rp2040-core0.cfg is totally unusable with a standard SWD
adapter. The file was marked as deprecated in 0.12 release.
The reworked rp2040.cfg can be restricted to use just one core:
openocd ... -c 'set USE_CORE 0' -f target/rp2040.cfg
Remove the obsoleted config.
Change-Id: Id886471622bb4a8cb83f5c4c3660657407aaaf74
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7326
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add the variable selected configuration for SMP debug with rtos hwthread.
Use SMP by default.
Change-Id: I1c37d91688a3ab58d65c15686737892965711adc
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7242
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The target nds32 and its companion adapter aice have not received
any real improvement since 2013.
It has been hard to keep them aligned during the evolution of
OpenOCD code, with no way for maintainers to really check if they
are still working.
No real documentation is present for them in OpenOCD.
The nds32 code triggers ~50 errors/warnings with scan-build.
The arch nds32 has been dropped from Linux kernel v5.18-rc1.
For all the reasons above, this code has been deprecated with
commit 2e5df83de7 ("nds32: deprecate it, together with aice
adapter driver") and tagged to be dropped before v0.13.0.
Let it r.i.p. in OpenOCD git history.
While there, drop from checkpatch list the camelcase symbols that
where only used in this code.
Change-Id: Ide52a217f2228e9da2f1cc5036c48f3536f26952
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7382
Tested-by: jenkins
The speed coefficient for Raspberry Pi 2 was probably calibrated
for a scaled down clock frequency.
To prevent JTAG/SWD overclocking, use the value corresponding
to the 'official' maximum CPU clock.
Change-Id: Iaff58b092198dce6d6552c9d31d6a3ba4aaaa2d5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7305
Tested-by: jenkins
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
The existing rp2040-core0.cfg configuration file was intended
for a special adapter which selects a SWD multidrop target on its own.
This means that rp2040-core0.cfg is totally unusable with a standard SWD
adapter.
To fix the problem, mark rp2040-core0.cfg as deprecated and
add rp2040.cfg, a basic config file with multidrop target selection.
Change-Id: I5194e42f529a2d9645481424b7c66ab61efa44ee
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7275
Tested-by: jenkins
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
instrument "target/stm32x5x_common.cfg" used by both STM32L5x/U5x
to support HLA adapters like "interface/stlink.cfg" in non-secure mode
if the device switches to secure mode, the debug session will be
stopped immediately (with an explanatory message).
Change-Id: I645fdd55e3448ef82d0ddcc396f42fd7b2f39ac3
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reported-by: Patrik Bachan <diggit@users.sourceforge.net>
Fixes: https://sourceforge.net/p/openocd/tickets/317/
Reviewed-on: https://review.openocd.org/c/openocd/+/6546
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Some config changes required to run ESP32-S3 with full feature set
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I38022bb5ff5830e1cf9d11d6fe795ea99d91e9db
Reviewed-on: https://review.openocd.org/c/openocd/+/7254
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Some config changes required to run ESP32-S2 with full feature set
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ie0a742442254ec6e95d4e05be40213b079a94dab
Reviewed-on: https://review.openocd.org/c/openocd/+/7253
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Some config changes required to run ESP32 with full feature set
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I484324f8497ec7934bb73164c638fc5f6460fcc4
Reviewed-on: https://review.openocd.org/c/openocd/+/7252
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The work area should be backed up.
The flash probe runs an algorithm on the target CPU.
The flash is probed during gdb connect if gdb_memory_map is enabled
(is enabled by default).
Without backup the target memory gets corrupted on gdb connect.
Change-Id: I3344b9dc6cbf904d49f3b05ab104b541d1d63422
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7257
Tested-by: jenkins
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Since all the device definition when accessing device from jtag is also
valid when accessing from swd, lets make sure the configuration can
handle the same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I5af071137fd8c3b52cc4ef72401f8eba952f9cad
Reviewed-on: https://review.openocd.org/c/openocd/+/7090
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The STM32L5 and U5 devices have DBGMCU_CR trace related bits changed
wrt other STM32 devices.
Fix the setting in configuration script.
Change-Id: I0bbc48e7b1290b603c6966cf5ddd42df389e6ede
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7117
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Use the new "adapter gpio" commands to configure the GPIOs used by the
bcm2835gpio driver. The driver supports only 1 chip (gpiochip0).
The reset function now honours the srst_open_drain and trst_open_drain
options.
Signed-off-by: Steve Marple <stevemarple@googlemail.com>
Change-Id: I5b6c68b16362000cf5141a83394549d2bf3af108
Reviewed-on: https://review.openocd.org/c/openocd/+/7123
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Still some config file uses deprecated commands.
Replace them with the new commands.
Change-Id: I6ccbfb832e0ad2012e9af160bd2d92ad104af2bb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7181
Tested-by: jenkins
- Config files for DAP/JTAG and DAP/SWD systems
- Xtensa core config definitions for NXP RT685 with Xtensa HiFi DSP
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I9c3280052073d86e09c7553de661eb8662a95c4a
Reviewed-on: https://review.openocd.org/c/openocd/+/7145
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
While reviewing on gerrit the change
https://review.openocd.org/6932/
it get clear that the missing documentation on stm32f4x's code
was triggering errors in the new change.
OpenOCD is currently unable to read traces, but these can be
hopefully be read with some other tool.
Document the settings for enabling trace on stm32[fl]4x.
Change-Id: Ibae77a53de16375d3d500e728678740095547009
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6945
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
With commit dc7b32ea4a ("armv7m_trace: get rid of the old tpiu
code") the target's event "trace-config" has been deprecated.
Create the TPIU device.
Replace the target's event "trace-config" with tpiu's event
"pre-enable" in the STM32 devices that require enabling the trace
clock _before_ programming the TPIU.
Make the script multi-instance-able in case it's used for JTAG
chained devices.
Uniform the code in STM32F4x with the other scripts.
Remove the empty event from STM32WLx.
Change-Id: Ifda219c3c5f37e03072a88168611cf505eb630b7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6681
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Generic Xtensa LX support extends the original Espressif/Xtensa
patch-set to support arbitrary Xtensa configurations, as defined in
a core-specific .cfg file. Not yet fully-featured. Additional
functionality to be added:
- Xtensa NX support
- DAP/SWD support
- File-IO support
- Generic Xtensa multi-core support
Valgrind-clean, no new Clang analyzer warnings
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I08e7bf8fa57c25b5d0cb75a1aa7a2ac13a380c52
Reviewed-on: https://review.openocd.org/c/openocd/+/7055
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Use the new "adapter gpio" commands to configure the GPIOs used by the
linuxgpiod driver.
Adds support for drive mode and resistor pull options on all signals.
Change-Id: Ic90cb4f06db82435294228b6793330107a9f3606
Signed-off-by: Steve Marple <stevemarple@googlemail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7048
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Use the new "adapter gpio" commands to configure the GPIOs used by the
am335xgpio driver. The AM335x has 4 GPIO 'chips' (chip number 0-3
inclusive), with each one providing 32 GPIOs (gpio_num 0-31 inclusive).
Change-Id: I7c63c0e4763657ea51790c43fc40d32b7c3580bb
Signed-off-by: Steve Marple <stevemarple@googlemail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6984
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This patch adds support for DAP interface to Cadence vdebug driver.
It implements a new transport layer for dapdirect_swd.
Change-Id: I64b02a9e1ce91e552e07fca692879655496f88b6
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6965
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This driver is used with the ESP32 chips which has builtin USB-JTAG
interface. e.g. with ESP32-C3, ESP32-S3
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: If966268cb8d26f76540dd5440245a17ed0b72c61
Reviewed-on: https://review.openocd.org/c/openocd/+/6943
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ief3da306a6e1978de7dfb8f552f9ff23151f9944
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7030
Tested-by: jenkins
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/interface | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: I7bd6a628e9e153fc477cddf9b97087a39ec48aa7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7029
Tested-by: jenkins
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/ target| while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: I7b2610300b24cccd07bfa6fb5f1266970d5d3a1b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7027
Tested-by: jenkins
The SPDX tag is aimed at machine handling and it's thus expected
to be placed in the first line.
Change-Id: I3992856eeb28b333c38d010ef286e22471ede263
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7026
Tested-by: jenkins
OpenOCD project is switching to SPDX tags.
Replace the few FSF boilerplate in tcl folder.
Change-Id: I15b146eb77cc491ed7355178f684f3e76fc763b4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7025
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
In order to facilitate debugging multiple cores, specify the coreid and
the hwthread rtos in the imx8m target configuration.
Change-Id: Ibd871517a160ceca15002fb10e27cb793f14d086
Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Reviewed-on: https://review.openocd.org/c/openocd/+/7019
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
ESP32-S3 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I44e17088030c96a9be9809f6579a4f16dbfc5794
Reviewed-on: https://review.openocd.org/c/openocd/+/6990
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
ESP32 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I76fb184aa38ab9f4e30290c038b5ff8850060750
Reviewed-on: https://review.openocd.org/c/openocd/+/6989
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add Ampere Altra ("Quicksilver") and Ampere Altra Max ("Mystique")
target/board configuration files.
The target configuration file supports silicon and emulation.
The board configuration files support 1 and 2 socket platforms.
Tested on Ampere emulation and silicon
Change-Id: I036c798a50624e30ab51ccd2895b6f60c40be096
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5591
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
ESP32-S2 is a single core Xtensa chip.
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I2fb32978e801af5aa21616c581691406ad7cd6bb
Reviewed-on: https://review.openocd.org/c/openocd/+/6940
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This commit is adapted from [1].
[1] https://review.openocd.org/c/openocd/+/4999
Signed-off-by: Michael Walle <michael.walle@kontron.com>
Signed-off-by: Heiko Thiery <heiko.thiery@kontron.com>
[ adapted to use common configuration ]
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I9a428371694e7864e03055b8de18a55a7843b8c2
Reviewed-on: https://review.openocd.org/c/openocd/+/6977
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The LS1028A is similar to the LS1088A, except that it has 2 CPUs (and
different ethernet capabilities). From a JTAG perspective, all that's
different is the number of CPUs and the TAPID.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: Iba3a0ecfbf82cfcfeb7eea42d52121c3b9dc93a2
Reviewed-on: https://review.openocd.org/c/openocd/+/6976
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Several Layerscape processors (LS1088A, LS2088A, LS2160A, and LS1028A)
share a common architecture. Break out the common setup from the LS1088
config in preparation for adding the LS1028A. There's no official name
for this series of processors, but NXP refers to them as "chassis
generation 3" in U-Boot, so we'll go with that too.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: Ic6f89f95c678101f54579bcaa5d79c5b67ddf50a
Reviewed-on: https://review.openocd.org/c/openocd/+/6975
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Added support for the new Renesas RISC-V
device: RZ/Five
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Change-Id: Id8ba29b83528c0bfe4f9b4ed21b0151a6e853bd7
Reviewed-on: https://review.openocd.org/c/openocd/+/6974
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Added support for two new devices: RZ/G2LC and RZ/G2UL
Change-Id: Iec6ba88c1d279f50808b060343b45c796bbfdbfc
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6972
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tigard[1] is an FT2232H-based development tool designed for ease of use
with many different protocols and targets. It includes a JTAG header
wired to channel B, with labeled pins for the four required signals as
well as nTRST and nSRST, which are connected through an output buffer to
BDBUS4 and BDBUS5 respectively.
Add an interface config for Tigard. I wrote it by referencing the Tigard
schematic and tested it by debugging a couple of RISC-V development
boards.
[1] https://github.com/tigard-tools/tigard
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Change-Id: I34df9f72538ba1e40ad53b568c9cdca96ae4b082
Reviewed-on: https://review.openocd.org/c/openocd/+/6952
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Added bluenrg-lps support
Added file for the board steval-idb012v1
Fixed size_info information using a mask
Changed the if condition in bluenrg-x.cfg to be valid only for bluenrg-1 and bluenrg-2
Signed-off-by: Salvatore Giorgio PECORINO <salvatore-giorgio.pecorino@st.com>
Change-Id: Ic0777ec0811ee6fac7d5e1d065c4629e47d84a1f
Reviewed-on: https://review.openocd.org/c/openocd/+/6928
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The flash is compatible with stm32f1x, reuse the driver.
Extend the size of work area to RAM size of the smallest device.
Stop watchdogs before flash programming.
Change-Id: I67a7654a6e196f9d4b2409edaa7990c53334437e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6711
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested on an EFM32PG12 Starter Kit.
Change-Id: I2cbc36fe0d2ad2089bf8c1e7d2260daaae4ddbb4
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/5353
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Replace deprecated commands 'mem2array' and 'array2mem' with
new Tcl commands 'read_memory' and 'write_memory'.
Change-Id: I116d995995396133ca782b14cce02bd1ab917a4e
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6859
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This adds support for the LS1046A Reference Design Board. There are
several JTAG headers accessable once the case is opened, but this config
is for the externally-accessable CMSIS DAP.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I0f83470da3758f0c4512ce47348c4db7de17b27e
Reviewed-on: https://review.openocd.org/c/openocd/+/6855
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The LS1046A is a quad-core processor from NXP in the layerscape family.
This SoC is a bit tricky to program: while the AArch64 CPUs are
little-endian, most of the peripherals are big-endian. Care must be
taken when interpreting memory reads/writes. This processor is in the
same family as the ls1012a, so the setup is similar.
If you use OpenOCD to attach early in the boot process, only the cpu0
may be available. Trying to halt other CPUs will fail. To avoid this,
defer examination of cpus 1-3, and provide a core_up helper (like e.g.
zynqmp).
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: If5a1a9441fb35fea3e05dc708b42e0cb3bbf2a54
Reviewed-on: https://review.openocd.org/c/openocd/+/6854
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Original TLC syntax uses 'set varname' to retrieve the value of
variable 'varname'. Such archaic syntax is still valid, but the
shorter '$varname' makes the code easier to read.
Replace 'set varname' with '$varname'.
While there, remove some useless curly brackets.
Change-Id: I27310e8c05afe56ea8bd0e41d4ae2c34447b725c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6863
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add support for the latest in TI k3 family AM625 SoC.
For further details, see https://www.ti.com/lit/pdf/spruiv7
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ia54d0eab1c30a973afb1c2c61f4c5a72d29d9b78
Reviewed-on: https://review.openocd.org/c/openocd/+/6798
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add support for the latest in TI k3 family J721S2 SoC.
For further details, see http://www.ti.com/lit/pdf/spruj28
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I608ab4513ffb6b5c4166ba423e7d0dddbbb3bbfd
Reviewed-on: https://review.openocd.org/c/openocd/+/6796
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Since we can detect the type of target as well, reuse the _cpu_no_smp_up
function name and use the target name to simplify the _up function and
maintain consistency with what we introduced for r5.
Lets introduce gdb-attach event in a much cleaner fashion.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
While at it, fix a minor type of s/are/as in "Set Default target are
core 0" and simplify the foreach usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I3259b7c3ae4c71b06d921edfaefe17c03bb673dc
Reviewed-on: https://review.openocd.org/c/openocd/+/6616
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Since we can detect the type of target as well, make the attach
function name generic for the follow on cleanup patch on armv8 to use
as well.
Lets introduce gdb-attach event in a much cleaner fashion. We can
introduce a simpler r5_up function since we now have more descriptive
core names making the individual descriptive procs redundant.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I31506bb2b86e63638082640eb72aa7c4c9575e93
Reviewed-on: https://review.openocd.org/c/openocd/+/6617
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
R5 targets are currently named r5.0..n and the only way for user to
determine the actual type is external documentation. Lets just rename
the target names to make them descriptive to not require external
documentation for finding which R5 to connect to.
NOTE: we leave the _mcu_r5_cores _main0_r5_cores _main1_r5_cores alone
for now to allow existing startup proc functions to work, but we will
drop it in the follow on patch.
Previously:
Info : starting gdb server for j721e.cpu.r5.0 on 3336
Info : Listening on port 3336 for gdb connections
Info : starting gdb server for j721e.cpu.r5.1 on 3337
Info : Listening on port 3337 for gdb connections
Info : starting gdb server for j721e.cpu.r5.2 on 3338
Info : Listening on port 3338 for gdb connections
Info : starting gdb server for j721e.cpu.r5.3 on 3339
Info : Listening on port 3339 for gdb connections
Info : starting gdb server for j721e.cpu.r5.4 on 3340
Info : Listening on port 3340 for gdb connections
Info : starting gdb server for j721e.cpu.r5.5 on 3341
Info : Listening on port 3341 for gdb connections
With this patch:
Info : starting gdb server for j721e.cpu.mcu_r5.0 on 3336
Info : Listening on port 3336 for gdb connections
Info : starting gdb server for j721e.cpu.mcu_r5.1 on 3337
Info : Listening on port 3337 for gdb connections
Info : starting gdb server for j721e.cpu.main0_r5.0 on 3338
Info : Listening on port 3338 for gdb connections
Info : starting gdb server for j721e.cpu.main0_r5.1 on 3339
Info : Listening on port 3339 for gdb connections
Info : starting gdb server for j721e.cpu.main1_r5.0 on 3340
Info : Listening on port 3340 for gdb connections
Info : starting gdb server for j721e.cpu.main1_r5.1 on 3341
Info : Listening on port 3341 for gdb connections
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I2989efe3ae3e16754f98fa1dc9363ec4c898f7c3
Reviewed-on: https://review.openocd.org/c/openocd/+/6627
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The MCU is present on few of the SoCs and is meant as General Purpose
(GP) MCU of the system. Lets rename it to make clear what we are
debugging - esp when multiple MCUs are present in the system.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I16132d321daf6e9b1d893fe6f92026d5aa9eb152
Reviewed-on: https://review.openocd.org/c/openocd/+/6619
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The M3 is the system controller of the system. Lets rename it to make
clear what we are debugging - esp when multiple MCUs are present in the
system.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I4cd03b6068b8ce140fd254f9dd88151c4c7006d7
Reviewed-on: https://review.openocd.org/c/openocd/+/6618
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add gdb-attach event to call the "up" function of m3 and m4 allowing for
more seamless integration with gdb for end users. We still retain _up
functions for non-gdb functionality.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I2e51fdbd8756f156551e589c748c3a338afa655c
Reviewed-on: https://review.openocd.org/c/openocd/+/6615
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
both stm32l5x and stm32u5x configs are almost identical except
clock config.
while at there rename target procs to avoid issues with JTAG daisy
chaining.
Change-Id: Ibbb1dfeb91a7f8d5d45744cf57dca2877f60e0c5
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6596
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
This adds a board file for the NXP LS1088ARDB. This only covers the
"primary" JTAG header J55, and not the PCIe header (J91). The only
oddity is that the LS1088A and CPLD are muxed by adding/removing a
jumper from J48. Unfortunately, it doesn't look like OpenOCD supports
this CPLD beyond determining the irlen, so it's not very useful. Those
who are interested in experimenting can define CWTAP to access the CPLD,
but the default is to access the CPU.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: Ia07436a534f86bd907aa5fe2a78a326a27855a24
Reviewed-on: https://review.openocd.org/c/openocd/+/6849
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Normally the service processor is not necessary for debugging. However,
if you are using the hard-coded RCW or your boot source is otherwise
corrupt, then the general purpose processors will never be released from
hold-off. This will cause GDB to become confused if it tries to attach,
since they will appear to be running arm32 processors. To deal with
this, we can release the CPUs manually with the BRRL register. This
register cannot be written to from the axi target, so we need to do it
from the service processor target. This involves halting the service
processor, modifying the register, and then resuming it again. We try
and determine what state the service processor was in to avoid resuming
it if it was already halted.
The reset vector for the general purpose processors is determined by the
boot logation pointer registers in the device configuration unit.
Normally these are set using pre-boot initialization commands, but if
they are not set then they default to 0. This will cause the CPU to
almost immediately hit an illegal instruction. This is fine because we
will almost certainly want to attach to the processor and load a program
anyway.
I considered adding this as an event handler for either gdb-attach or
reset-init. However, this command shouldn't be necessary most of the
time, and so I don't think we should run it automatically.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I1b725292d8a11274d03af5313dc83678e10e944c
Reviewed-on: https://review.openocd.org/c/openocd/+/6850
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The LS1088A is an octo-core aarch64 processor from NXP in the layerscape
family. The JTAG is undocumented, but I was able to figure things out
from the output of `dap info`. This is the first in-tree example of
using the hwthread rtos (as far as I know), so hopefully it can serve as
an example to other developers. There are some ETMs, but I was unable to
try them out because I got 'invalid command name "etm"' when trying to
test things out.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I9b0791d27d8c41170a413a8d86431107a85feba2
Reviewed-on: https://review.openocd.org/c/openocd/+/6848
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
According to the datasheet, the minimum clock period with Vccio1 = 1.5V
(the lowest voltage supported) is 143ns, or around 6MHz. Set the default
adapter speed to 5 MHz.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de
Reviewed-on: https://review.openocd.org/c/openocd/+/6847
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This adds some additional IDCODEs from the datasheet. It also adds
support for customizing the tap name.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e
Reviewed-on: https://review.openocd.org/c/openocd/+/6846
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Changed flash driver to support writing to the user data page, as well as to any portion of the lockbits page above 512 bytes (the amount used for the actual page lock words). The top part of the lockbits page is used on at least the EFR32xG1 chips for the SiLabs bootloader encryption keys.
As presented to the user, the lockbits page is the same size as the other pages, but any attempt to write to its low 512 bytes is an error. To enforce this, efr32x_write is renamed to efm32x_priv_write and a wrapper function is provided in its place. If the user erases the lockbits page, the driver rewrites the cached lock words after the erase. When the driver erases the lockbits page in order to update the lock words, it first takes a copy of anything stored in the top part of the page, and re-programs it after the erase operation.
There are now multiple instances of flash_bank for each target, and the flash_bank instances must share their cached lock words to operate as intended. Therefore, when a bank is created, the global flash bank list is used to find any other banks that share the same target. Since some banks in the global list are invalid at the time free_driver_priv is called, reference counting is used to decide when to free driver_priv.
To avoid the need to find the lockbits flash_bank from another flash_bank, efm32x_priv_write and efm32x_erase_page now take an absolute address.
There didn't seem to be any reason to prohibit unprotecting individual flash pages, so that limitation is removed from efm32x_protect().
This addresses ticket #185.
Valgrind-clean, except for 2x 4kiB not freed/still reachable blocks that were allocated by libudev.
No new Clang analyzer warnings, no new sanitizer warnings.
Signed-off-by: Doug Brunner <doug.a.brunner@gmail.com>
Change-Id: Ifb22e6149939d893f386706e99b928691ec1d41b
Reviewed-on: https://review.openocd.org/c/openocd/+/6665
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik.hederstierna@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This board is (software wise) similar to the existing SAME54 Xplained
Pro board, with just a slightly different MCU. (Hardware wise, it
features a vastly different form factor.)
Signed-off-by: Jörg Wunsch <openocd@uriah.heep.sax.de>
Change-Id: I5e5435d49d333fb74471994ee84de59ed983153c
Reviewed-on: https://review.openocd.org/c/openocd/+/6747
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Axel W.
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The stm32mp13x has one core Cortex-A7.
The board Discovery Kit includes an on-board STLink-V3 with SWD
connection.
The webpage of the board is not active yet.
Change-Id: I8836b26612a160ead79766955ebefaf3d21a329c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6675
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The driver hla defines the command 'hla_serial' to specify the
serial string of the adapter.
The driver st-link defines the command 'st-link serial' to specify
the serial string of the adapter.
Remove and deprecate the driver commands and use 'adapter serial'.
Change-Id: I9505c398a77125b1ebf4ba71da7baf4d663b75be
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6657
Tested-by: jenkins
The driver jlink defines the command 'jlink serial' to specify the
serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Note: in former code the commands 'jlink serial' and 'jlink usb'
were mutually exclusive; running one of them would invalidate the
effect of a previous execution of the other. The new code gives
priority to 'adapter serial', even if executed before 'jlink usb'.
Change-Id: I920b0c136716f459b6fd6f7da8a01a7fa1ed389f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6656
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
The driver xds110 defines the command 'xds110 serial' to specify
the serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Note: the original command 'xds110 serial' used a complex and
undocumented conversion of the serial number through multibyte
string, wide-character string and C cast. The XDS110 I can access
and the lsusb dumps available through Google don't show any
exotic USB serial that require such conversion. The original
developer doesn't remember any constraint that mandates such
conversion (see comments in https://review.openocd.org/4322/).
The conversion is removed by this patch.
Change-Id: I38909918079b2c1797ad85ebec2fea1b33743606
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6655
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The driver kitprog defines the command 'kitprog_serial' to specify
the serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Change-Id: I844cb815af01137392b6d12e1b5972fc77ac092d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6652
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The driver ftdi defines the command 'ftdi serial' to specify the
serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Change-Id: Ia5b1f325b9fab8f58b5ea70f8b807e50b148b939
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6651
Tested-by: jenkins
The driver cmsis_dap defines the command 'cmsis_dap_serial' to
specify the serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Change-Id: I88e2d4de360a6c6f23529bb18494962a267250df
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6649
Tested-by: jenkins
The driver aice defines the command 'aice serial' to specify the
serial string of the adapter, but actually does not use this value
in the code.
Remove and deprecate the driver command, and use 'adapter serial'.
Change-Id: I892e0a4e1b41a7a87adf54a5736abf7419f32979
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6648
Tested-by: jenkins
GD32E23x from GigaDevice is cortex-M23 microcontroller and it can work with the stm32f1x driver.
Modifications are similar to this done for GD32F1x0 in #6164 (https://review.openocd.org/c/openocd/+/6164).
Configuration file is added because its cortex-M23 CPU ID is different.
I think that GigaDevice microcontrollers should be handled in an independent unit to separate them from STM32,
but nowadays quick solution is welcome.
Signed-off-by: asier70Andrzej Sierżęga <asier70@gmail.com>
Change-Id: I91f31f5f66808bc50a8f607ac2c107e6b7c5e2b8
Reviewed-on: https://review.openocd.org/c/openocd/+/6527
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Freeze the IWDG watchdog when cores are halted to prevent a reset
while debugging.
The PMIC present on some board senses the nsrst and forces a power
cycle to the target. The power cycle causes the SWJ-DP to restart
in JTAG mode. If the debugger is using SWD, the mismatch triggers
an error after the reset command.
Ignore the error detected by 'dap init' and proceed executing the
handler. The error in 'dap init' will force a reconnect during the
following 'dap apid', restoring the SWD functionality.
Change-Id: I04fcda6a5b8a1b080ab4e8890ecd0754d5ed12d9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6599
Tested-by: jenkins
Add the 0x3754 PID used by some STLINK-V3 devices when MSD has been
disabled. This PID has been observed on a Nucleo-G431RB board.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Change-Id: Idb85874fa5a9dff5940bae7e95426a956693b976
Reviewed-on: https://review.openocd.org/c/openocd/+/6555
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
do not force the presence of the reset line, since some custom boards
may do not contain the reset line.
Change-Id: I031ab34012b34a1b49def9db16461f9de0ae29cc
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reported-by: Fleck <fleckz@users.sourceforge.net>
Fixes: https://sourceforge.net/p/openocd/tickets/316/
Reviewed-on: https://review.openocd.org/c/openocd/+/6506
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
known boards are NUCLEO-G431KB, NUCLEO-G431RB and NUCLEO-G474RE
note: this work safely with B-G431B-ESC1, B-G474E-DPOW1,
STM32G474E-EVAL and STM32G484E-EVAL
Change-Id: I132a97e1816620b182983edc8a4b272b52b9241d
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5484
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
known boards are NUCLEO-G031K8, NUCLEO-G070RB, NUCLEO-G071RB
note: this work safely with STM32G0316-DISCO, STM32G071B-DISCO
and STM32G081B-EVAL
Change-Id: I483b6f44409228cd8c2c97b3c560927d1645c517
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5483
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
this device flash registers are quite similar to STM32L5
with this changes :
- flash size is up to 2MB
- 2MB variants are always dual bank
- 1MB and 512KB variants could be dual bank (contiguous addressing)
depending on DUALBANK bit(21)
- flash data width is 16 bytes (quad-word)
Change-Id: Id13c552270ce1071479ad418526e8a39ebe83cb1
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6108
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
according the RM0453, the second core have a different Flash CR and SR
registers for flash operations (called C2CR and C2SR).
so we need to a different flash_regs than older L4 devices.
@see stm32wl_cpu2_flash_regs
the C2CR register don't contain LOCK and OPTLOCK bits, and this explain
the addition of new register index called STM32_FLASH_CR_WLK_INDEX to
look-up the CR with lock, to be used in locking/unlocking the flash.
note: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
to solve this read the UID64 (IEEE 64-bit unique device ID register)
Change-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6050
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
when RDP level is 0.5 the provided work-area should reside in non-secure RAM
to ensure that:
- add a hint in the driver level
- reduce the usage of secure RAM only when TZEN=1 and RDP is not 0.5
(check the target configuration file)
Change-Id: Idbf2325e609b84ef8480eefdb49a176fdf7e07c7
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6035
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
STM32L5 flash memory is aliased to 0x0C000000, this address mapping
is used for secure applications. (0x08000000 for non-secure)
this change allows the programming of secure and non-secure flash
when trustzone is enabled and RDP level is 0
Change-Id: I89d1f1b5d493cf01a142ca4dbfef5a3731cab96e
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5936
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Add support for ECP5 FPGA targets and board based on this chips:
Radiona ULX3S and Lambdaconcept ECPIX-5
Change-Id: I932fc6e2458cda7d63ac21579acddea5b53410bc
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6112
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
OpenOCD cannot connect to BCM2711's JTAG interface on RPi 4B board until
the reset configuration mode is set as trst_only.
According to Table 94. GPIO Pins Alternative Function Assignment of
Broadcom's BCM2711 ARM Peripherals datasheet [1] and Raspberry Pi's GPIO
control in config.txt document [2], only Test Reset (TRST) pin (no
System Reset, SRST) is exposed.
[1] https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
[2] https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md
Change-Id: I806f0be9700fa0f0944b42c8a651a5731adc762b
Link: http://openocd.zylin.com/#/c/6364/1
Signed-off-by: Jian-Hong Pan <chienhung.pan@gmail.com>
Reviewed-on: http://openocd.zylin.com/6367
Tested-by: jenkins
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This adds support for the Blinkinlabs JTAG Hat, a Raspberry Pi
expansion board that provides JTAG and SWD connections via level-
shifting buffers.
Change-Id: I228bf6a18890b7c3d6679bbc63bfe39f726d8323
Signed-off-by: Matthew Mets <matt@blinkinlabs.com>
Reviewed-on: http://openocd.zylin.com/6372
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Drive the output enable for TMS and TDI
Change-Id: Ib23afd2f5149d4ce402d88781e68dcf0f074f395
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Reviewed-on: http://openocd.zylin.com/4179
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The legacy ft2232 driver suggests that the adapter has tristate
buffers on both nSRST and nTRST, even though they were not used as
such.
Change-Id: I971692ea6b3439ac93311b89877825a5cc21df46
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3663
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The Flyswatter URL is dead and requires us to use web.archive.org since
the product is discontinued. The Flyswatter 2 is still active and
accessible at a different URL.
Change-Id: Ib2d9de70a9728b0f0ef73f5e479bca81f958442c
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-on: http://openocd.zylin.com/6337
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add board configuration for Renesas Falcon board based on the R8A779A0 V3U SoC.
Change-Id: If8369f2e2b97dfea9ccbee2c9b916ef7094f9b92
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/6315
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The V3U SoC is unique in that it now has 8x CA76 and CR52,
while the previous SoCs had CA57/CA53/CR7 . This can still
be handled without too complex modifications to the gen3
configuration file, so add the logic to handle it there.
Change-Id: I7ab33eacc1fd379d369988d3d6690d2e82346c7e
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/6314
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
On SMP Renesas R-Car Gen2/Gen3 systems, select the boot core as
the default target using the 'targets' command. This way, the
user can start debugging code running on the boot core without
having to switch to the boot core by explicitly invoking 'targets'
command first, since it is likely the debugged code will run on
the boot core. Note that most of the code is already in place, it
was just not used, so this is more of a fix to make the original
intention work.
Change-Id: I727808adce617c1d9ebd6ffa34f60f5882cdae60
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/6313
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Initial support for Renesas RZ/G2 MPU family
Change-Id: I5ca74cddfd0c105a5307de56c3ade7084f9c28d2
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Reviewed-on: http://openocd.zylin.com/6250
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
There are still few adapter_khz, ftdi_location, jtag_nsrst_delay
and xds110_serial strolling around ...
Change-Id: I3e8503dcc3875e3c92e6536f3d455a5e448d51ff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6270
Tested-by: jenkins
The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs.
Change-Id: I6303331c217795657575de4759444938e775dee1
Signed-off-by: Olivier DANET <odanet@caramail.com>
Reviewed-on: http://openocd.zylin.com/6263
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.
While there, fix one indentation.
Change-Id: I72369ed26f363bacd760b40b8c83dd95e89d28a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6214
Tested-by: jenkins
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.
Fix manually the remaining lines that don't match simple patterns
and would require dedicated boring scripting.
Remove the 'expr' command where appropriate.
Change-Id: Ia75210c8447f88d38515addab4a836af9103096d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6161
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.
Enclose within double quote the argument of 'expr' when there is
the need to concatenate strings.
Change-Id: Ic0ea990ed37337a7e6c3a99670583685b570b8b1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6160
Tested-by: jenkins
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.
In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.
Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
#!/usr/bin/perl -Wpi
my $re_sym = qr{[a-z_][a-z0-9_]*}i;
my $re_var = qr{(?:\$|\$::)$re_sym};
my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
my $re_op = qr{<<|>>|[+\-*/&|]};
my $re_expr = qr{(
(?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
\s*$re_op\s*
(?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
)}x;
# [expr [dict get $regsC100 SYM] + HEXNUM]
s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;
# [ expr (EXPR) ]
# [ expr EXPR ]
# note: $re_expr captures '$3'
s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
pico-debug is not a board; it is a virtual CMSIS-DAP adapter that
runs on the same RP2040 also being debugged. This is possible due
to pico-debug running on the normally-dormant second Cortex-M0+
core (Core1), providing debugging of the first core (Core0).
As such, it could be used on a variety of RP2040-based boards.
Since a flash driver is useful (if not essential), a flash driver
is included. This driver code originated on RPi's bespoke OpenOCD
fork; lipstick was added to this particular pig to make it more
presentable on OpenOCD proper.
no new Clang analyzer warnings
Change-Id: I31f98b5ea1664f0adfbc184b57efba963acfb958
Signed-off-by: Peter Lawrence <majbthrd@gmail.com>
Reviewed-on: http://openocd.zylin.com/6075
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This file has been added to OpenOCD 0.5.0 in 2011, before gerrit
gets in use, with commit ba71e8c521 ("at91: add chip register
definition and generic init support").
The only procedure in the file has never been referenced in any
other part of OpenOCD. This procedure has syntax errors while uses
its argument 'cs' and several unmatched parenthesis, which clearly
highlights that it has never been used so far.
Gerrit does not report any patch aimed at fixing it.
Even if the file seems unused and could be removed, let's fix it
in the hope it could get used.
While there, remove some useless parenthesis and format it using
the new simplified syntax required by jimtcl 0.81.
Change-Id: Ied26456262e7b99de37667a8ce418f4f12e237bd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: ba71e8c521 ("at91: add chip register definition and generic init support")
Reviewed-on: http://openocd.zylin.com/6157
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Both http://openocd.zylin.com/542/ and http://openocd.zylin.com/543/
introduce the same typo in the bitfield for initializing the l2
cache of imx53.
One year later, http://openocd.zylin.com/1461/ copy-pastes the same
typo.
The comment above the code show that it's really an error and not
the expected behaviour.
Fix the typo replacing the incorrect comparison '<' with a left
shift.
Change-Id: I43725731a2228e28a676215f76936fa289d9395e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: e3b3273433 ("cfg: add imx53loco board config")
Fixes: 108a458ab8 ("cfg: add icnova_imx53_sodimm board config")
Fixes: e608ced330 ("ftdi/board: Add support for DENX M53EVK")
Reviewed-on: http://openocd.zylin.com/6156
Tested-by: jenkins
Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Chip is similar to imx8x series but has different cores at different
addresses.
Support for reduced versions is not yet available.
Tested on imx8qm-mek board
Change-Id: Ia34a80d561ab2849a570d8c375b936a45cbf45ca
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Oliver Graute <oliver.graute@kococonnector.com>
Reviewed-on: http://openocd.zylin.com/5042
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Zale Yu
Tomas Vanek
Kyle Schwarz
Antonio Borneo
Rocco Marco Guglielmi
George Voicu
Tarek BOCHKATI
Erhan Kurubas
Nishanth Menon
Paul Fertser
Steve Marple
Ian Thompson
Toms Stūrmanis
Jae Hyun Yoo
Jacek Wuwer
Adrien Grassein
Alvin Šipraga
Daniel Goehring
Sean Anderson
micbis
Thomas Hebb
Salvatore Giorgio PECORINO
Markus Reiter
Marc Schink
Hans-Erik Floryd
Doug Brunner
Joerg Wunsch
asier70
Andreas Sandberg
Wealian Liao
Oleksij Rempel
Ranjith Chandran
Jian-Hong Pan
Matthew Mets
Patrick Stewart
Andreas Fritiofson
Florian Fainelli
Marek Vasut
Rohit Singh
Olivier DANET
Peter Lawrence
Leonard Crestez