flash/stm32l4x: add support of STM32U57x/U58x
this device flash registers are quite similar to STM32L5 with this changes : - flash size is up to 2MB - 2MB variants are always dual bank - 1MB and 512KB variants could be dual bank (contiguous addressing) depending on DUALBANK bit(21) - flash data width is 16 bytes (quad-word) Change-Id: Id13c552270ce1071479ad418526e8a39ebe83cb1 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6108 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This commit is contained in:
Tarek BOCHKATI
Oleksij Rempel
parent
6c1e1a212a
commit
c2ad18d68b
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@ -7302,7 +7302,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
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@end deffn
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@deffn {Flash Driver} {stm32l4x}
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All members of the STM32 G0, G4, L4, L4+, L5, WB and WL
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All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
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microcontroller families from STMicroelectronics include internal flash
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and use ARM Cortex-M0+, M4 and M33 cores.
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The driver automatically recognizes a number of these chips using
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@ -133,6 +133,9 @@
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#define F_HAS_TZ BIT(2)
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/* this flag indicates if the device has the same flash registers as STM32L5 */
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#define F_HAS_L5_FLASH_REGS BIT(3)
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/* this flag indicates that programming should be done in quad-word
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* the default programming word size is double-word */
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#define F_QUAD_WORD_PROG BIT(4)
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/* end of STM32L4 flags ******************************************************/
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@ -236,6 +239,7 @@ struct stm32l4_flash_bank {
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bool dual_bank_mode;
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int hole_sectors;
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uint32_t user_bank_size;
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uint32_t data_width;
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uint32_t cr_bker_mask;
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uint32_t sr_bsy_mask;
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uint32_t wrpxxr_mask;
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@ -265,7 +269,7 @@ struct stm32l4_wrp {
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};
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/* human readable list of families this drivers supports (sorted alphabetically) */
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static const char *device_families = "STM32G0/G4/L4/L4+/L5/WB/WL";
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static const char *device_families = "STM32G0/G4/L4/L4+/L5/U5/WB/WL";
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static const struct stm32l4_rev stm32_415_revs[] = {
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{ 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
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@ -323,6 +327,10 @@ static const struct stm32l4_rev stm32_479_revs[] = {
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{ 0x1000, "A" },
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};
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static const struct stm32l4_rev stm32_482_revs[] = {
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{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
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};
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static const struct stm32l4_rev stm32_495_revs[] = {
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{ 0x2001, "2.1" },
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};
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@ -504,6 +512,18 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
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.otp_base = 0x1FFF7000,
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.otp_size = 1024,
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},
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{
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.id = 0x482,
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.revs = stm32_482_revs,
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.num_revs = ARRAY_SIZE(stm32_482_revs),
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.device_str = "STM32U57/U58xx",
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.max_flash_size_kb = 2048,
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.flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
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.flash_regs_base = 0x40022000,
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.fsize_addr = 0x0BFA07A0,
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.otp_base = 0x0BFA0000,
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.otp_size = 512,
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},
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{
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.id = 0x495,
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.revs = stm32_495_revs,
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@ -559,10 +579,6 @@ FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
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return ERROR_FAIL; /* Checkme: What better error to use?*/
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bank->driver_priv = stm32l4_info;
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/* The flash write must be aligned to a double word (8-bytes) boundary.
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* Ask the flash infrastructure to ensure required alignment */
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bank->write_start_alignment = bank->write_end_alignment = 8;
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stm32l4_info->probed = false;
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stm32l4_info->otp_enabled = false;
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stm32l4_info->user_bank_size = bank->size;
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@ -1297,11 +1313,12 @@ static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first,
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return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
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}
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/* Count is in double-words */
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/* count is the size divided by stm32l4_info->data_width */
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static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t offset, uint32_t count)
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{
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struct target *target = bank->target;
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struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
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uint32_t buffer_size;
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struct working_area *write_algorithm;
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struct working_area *source;
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@ -1328,7 +1345,11 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
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return retval;
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}
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/* memory buffer, size *must* be multiple of dword plus one dword for rp and one for wp */
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/* memory buffer, size *must* be multiple of stm32l4_info->data_width
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* plus one dword for rp and one for wp */
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/* FIXME, currently only STM32U5 devices do have a different data_width,
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* but STM32U5 device flash programming does not go through this function
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* so temporarily continue to consider the default data_width = 8 */
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buffer_size = target_get_working_area_avail(target) & ~(2 * sizeof(uint32_t) - 1);
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if (buffer_size < 256) {
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LOG_WARNING("large enough working area not available, can't do block memory writes");
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@ -1360,7 +1381,7 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
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buf_set_u32(reg_params[4].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX));
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buf_set_u32(reg_params[5].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX));
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retval = target_run_flash_async_algorithm(target, buffer, count, 8,
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retval = target_run_flash_async_algorithm(target, buffer, count, stm32l4_info->data_width,
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0, NULL,
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ARRAY_SIZE(reg_params), reg_params,
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source->address, source->size,
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@ -1396,10 +1417,11 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
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return retval;
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}
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/* Count is in double-words */
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/* count is the size divided by stm32l4_info->data_width */
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static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t offset, uint32_t count)
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{
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struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
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struct target *target = bank->target;
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uint32_t address = bank->base + offset;
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int retval = ERROR_OK;
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@ -1417,8 +1439,9 @@ static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uin
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/* write directly to flash memory */
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const uint8_t *src = buffer;
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const uint32_t data_width_in_words = stm32l4_info->data_width / 4;
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while (count--) {
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retval = target_write_memory(target, address, 4, 2, src);
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retval = target_write_memory(target, address, 4, data_width_in_words, src);
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if (retval != ERROR_OK)
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return retval;
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@ -1427,8 +1450,8 @@ static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uin
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if (retval != ERROR_OK)
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return retval;
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src += 8;
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address += 8;
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src += stm32l4_info->data_width;
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address += stm32l4_info->data_width;
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}
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/* reset PG in FLASH_CR */
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@ -1455,10 +1478,13 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
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return ERROR_TARGET_NOT_HALTED;
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}
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/* The flash write must be aligned to a double word (8-bytes) boundary.
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/* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
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assert(stm32l4_info->data_width % 8 == 0);
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/* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
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* The flash infrastructure ensures it, do just a security check */
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assert(offset % 8 == 0);
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assert(count % 8 == 0);
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assert(offset % stm32l4_info->data_width == 0);
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assert(count % stm32l4_info->data_width == 0);
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/* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
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* data to be written does not go into a gap:
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@ -1520,6 +1546,12 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
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if ((stm32l4_info->part_info->id == 0x467) && stm32l4_info->dual_bank_mode) {
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LOG_INFO("Couldn't use the flash loader in dual-bank mode");
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use_flashloader = false;
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} else if (stm32l4_info->part_info->id == 0x482) {
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/**
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* FIXME the current flashloader does not support writing in quad-words
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* which is required for STM32U5 devices.
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*/
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use_flashloader = false;
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}
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if (use_flashloader) {
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@ -1530,15 +1562,16 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
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if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
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LOG_INFO("RDP level is 0.5, the work-area should reside in non-secure RAM");
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retval = stm32l4_write_block(bank, buffer, offset, count / 8);
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retval = stm32l4_write_block(bank, buffer, offset,
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count / stm32l4_info->data_width);
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}
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if (!use_flashloader || retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
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LOG_INFO("falling back to single memory accesses");
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retval = stm32l4_write_block_without_loader(bank, buffer, offset, count / 8);
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retval = stm32l4_write_block_without_loader(bank, buffer, offset,
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count / stm32l4_info->data_width);
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}
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err_lock:
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retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
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@ -1657,9 +1690,14 @@ static int stm32l4_probe(struct flash_bank *bank)
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stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
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stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
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stm32l4_info->data_width = (part_info->flags & F_QUAD_WORD_PROG) ? 16 : 8;
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stm32l4_info->cr_bker_mask = FLASH_BKER;
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stm32l4_info->sr_bsy_mask = FLASH_BSY;
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/* Set flash write alignment boundaries.
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* Ask the flash infrastructure to ensure required alignment */
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bank->write_start_alignment = bank->write_end_alignment = stm32l4_info->data_width;
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/* initialise the flash registers layout */
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if (part_info->flags & F_HAS_L5_FLASH_REGS)
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stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
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@ -1852,6 +1890,18 @@ static int stm32l4_probe(struct flash_bank *bank)
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stm32l4_info->bank1_sectors = num_pages / 2;
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}
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break;
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case 0x482: /* STM32U57/U58xx */
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/* if flash size is max (2M) the device is always dual bank
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* otherwise check DUALBANK bit(21)
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*/
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page_size_kb = 8;
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num_pages = flash_size_kb / page_size_kb;
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stm32l4_info->bank1_sectors = num_pages;
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if ((flash_size_kb == part_info->max_flash_size_kb) || (stm32l4_info->optr & BIT(21))) {
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stm32l4_info->dual_bank_mode = true;
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stm32l4_info->bank1_sectors = num_pages / 2;
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}
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break;
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case 0x495: /* STM32WB5x */
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case 0x496: /* STM32WB3x */
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/* single bank flash */
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@ -114,9 +114,10 @@ proc stm32f7x args { eval stm32f2x $args }
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proc stm32l0x args { eval stm32lx $args }
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proc stm32l1x args { eval stm32lx $args }
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# stm32[g0|g4|wb|wl] uses the same flash driver as the stm32l4x
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# stm32[g0|g4|l5|u5|wb|wl] uses the same flash driver as the stm32l4x
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proc stm32g0x args { eval stm32l4x $args }
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proc stm32g4x args { eval stm32l4x $args }
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proc stm32l5x args { eval stm32l4x $args }
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proc stm32u5x args { eval stm32l4x $args }
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proc stm32wbx args { eval stm32l4x $args }
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proc stm32wlx args { eval stm32l4x $args }
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@ -0,0 +1,207 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32u5x family
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#
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# stm32u5 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32u5x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0438
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# RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
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# Corresponds to Cortex®-M33 JTAG debug port ID code
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set _CPUTAPID 0x0ba04477
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} {
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# SWD IDCODE (single drop, arm)
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set _CPUTAPID 0x0be12477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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# use non-secure RAM by default
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# create sec/ns flash and otp memories (sizes will be probed)
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flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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# the safe side.
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#
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# Note that there is a pretty wide band where things are
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# more or less stable, see http://openocd.zylin.com/#/c/3366/
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adapter speed 500
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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proc is_secure {} {
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# read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
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set DSCSR [mrw 0xE000EE08]
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return [expr {($DSCSR & (1 << 16)) != 0}]
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}
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proc clock_config_160_mhz {} {
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set offset [expr {[is_secure] ? 0x10000000 : 0}]
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# MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL
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# Enable voltage range 1 for frequency above 100 Mhz
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# RCC_AHB3ENR = PWREN
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mww [expr {0x46020C94 + $offset}] 0x00000004
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# delay for register clock enable (read back reg)
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mrw [expr {0x56020C94 + $offset}]
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# PWR_VOSR : VOS Range 1
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mww [expr {0x4602080C + $offset}] 0x00030000
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# delay for register write (read back reg)
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mrw [expr {0x4602080C + $offset}]
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# FLASH_ACR : 4 WS for 160 MHz HCLK
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mww [expr {0x40022000 + $offset}] 0x00000004
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# RCC_PLL1CFGR => PLL1M=0000=/1, PLL1SRC=MSI 4MHz
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mww [expr {0x46020C28 + $offset}] 0x00000001
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# RCC_PLL1DIVR => PLL1P=PLL1Q=PLL1R=000001=/2, PLL1N=0x4F=80
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# fVCO = 4 x 80 /1 = 320
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# SYSCLOCK = fVCO/PLL1R = 320/2 = 160 MHz
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mmw [expr {0x46020C34 + $offset}] 0x0000004F 0
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# RCC_PLL1CFGR => PLL1REN=1
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mmw [expr {0x46020C28 + $offset}] 0x00040000 0
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# RCC_CR |= PLL1ON
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mmw [expr {0x46020C00 + $offset}] 0x01000000 0
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# while !(RCC_CR & PLL1RDY)
|
||||
while {!([mrw [expr {0x46020C00 + $offset}]] & 0x02000000)} {}
|
||||
# RCC_CFGR1 |= SW_PLL
|
||||
mmw [expr {0x46020C1C + $offset}] 0x00000003 0
|
||||
# while ((RCC_CFGR1 & SWS) != PLL)
|
||||
while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}
|
||||
}
|
||||
|
||||
proc ahb_ap_non_secure_access {} {
|
||||
# SPROT=1=Non Secure access, Priv=1
|
||||
[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
|
||||
}
|
||||
|
||||
proc ahb_ap_secure_access {} {
|
||||
# SPROT=0=Secure access, Priv=1
|
||||
[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
clock_config_160_mhz
|
||||
# Boost JTAG frequency
|
||||
adapter speed 4000
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-start {
|
||||
# Reset clock is MSI (4 MHz)
|
||||
adapter speed 480
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event examine-end {
|
||||
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
|
||||
mmw 0xE0044004 0x00000006 0
|
||||
|
||||
# Stop watchdog counters during halt
|
||||
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
|
||||
mmw 0xE0044008 0x00001800 0
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event halted {
|
||||
set secure [is_secure]
|
||||
|
||||
if {$secure} {
|
||||
set secure_str "Secure"
|
||||
ahb_ap_secure_access
|
||||
} else {
|
||||
set secure_str "Non-Secure"
|
||||
ahb_ap_non_secure_access
|
||||
}
|
||||
|
||||
# print the secure state only when it changes
|
||||
set _TARGETNAME [target current]
|
||||
global $_TARGETNAME.secure
|
||||
|
||||
if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
|
||||
echo "CPU in $secure_str state"
|
||||
# update saved security state
|
||||
set $_TARGETNAME.secure $secure
|
||||
}
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event gdb-flash-erase-start {
|
||||
set use_secure_workarea 0
|
||||
# check if FLASH_OPTR.TZEN is enabled
|
||||
set FLASH_OPTR [mrw 0x40022040]
|
||||
if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
|
||||
echo "TZEN option bit disabled"
|
||||
ahb_ap_non_secure_access
|
||||
} else {
|
||||
ahb_ap_secure_access
|
||||
echo "TZEN option bit enabled"
|
||||
|
||||
# check if FLASH_OPTR.RDP is not Level 0.5
|
||||
if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
|
||||
set use_secure_workarea 1
|
||||
}
|
||||
}
|
||||
|
||||
set _TARGETNAME [target current]
|
||||
set workarea_addr [$_TARGETNAME cget -work-area-phys]
|
||||
echo "workarea_addr $workarea_addr"
|
||||
|
||||
if {$use_secure_workarea} {
|
||||
set workarea_addr [expr {$workarea_addr | 0x10000000}]
|
||||
} else {
|
||||
set workarea_addr [expr {$workarea_addr & ~0x10000000}]
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -work-area-phys $workarea_addr
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event trace-config {
|
||||
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
|
||||
# change this value accordingly to configure trace pins
|
||||
# assignment
|
||||
mmw 0xE0044004 0x00000020 0
|
||||
}
|
||||
Loading…
Reference in New Issue