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cpld: altera-epm240: Increase adapter speed 

According to the datasheet, the minimum clock period with Vccio1 = 1.5V
(the lowest voltage supported) is 143ns, or around 6MHz. Set the default
adapter speed to 5 MHz.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de
Reviewed-on: https://review.openocd.org/c/openocd/+/6847
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Sean Anderson 2022-02-11 17:43:30 -05:00 committed by Antonio Borneo
parent d673521c39
commit b61eae1962
1 changed files with 4 additions and 0 deletions
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tcl/cpld/altera-epm240.cfg
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@ -17,3 +17,7 @@ jtag newtap $_CHIPNAME tap -irlen 10 \
-expected-id 0x020a40dd \
-expected-id 0x020a50dd \
-expected-id 0x020a60dd
# 200ns seems like a good speed
# c.f. Table 5-34: MAX II JTAG Timing Parameters
adapter speed 5000