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tcl/stm32u5x: fix clock config used at 'reset init' 

Change-Id: If004a04b93be47439809ea3fa336b14de7a12277
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6597
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
This commit is contained in:
Tarek BOCHKATI 2021-09-16 17:47:31 +01:00 committed by Antonio Borneo
parent 414c469cda
commit 9cdbe61aab
1 changed files with 12 additions and 9 deletions
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21
tcl/target/stm32u5x.cfg
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@ -22,21 +22,24 @@ proc stm32u5x_clock_config {} {
# RCC_AHB3ENR = PWREN
mww [expr {0x46020C94 + $offset}] 0x00000004
# delay for register clock enable (read back reg)
mrw [expr {0x56020C94 + $offset}]
mrw [expr {0x46020C94 + $offset}]
# PWR_VOSR : VOS Range 1
mww [expr {0x4602080C + $offset}] 0x00030000
# delay for register write (read back reg)
mrw [expr {0x4602080C + $offset}]
mmw [expr {0x4602080C + $offset}] 0x00030000 0
# while !(PWR_VOSR & VOSRDY)
while {!([mrw [expr {0x4602080C + $offset}]] & 0x00008000)} {}
# FLASH_ACR : 4 WS for 160 MHz HCLK
mww [expr {0x40022000 + $offset}] 0x00000004
# RCC_PLL1CFGR => PLL1M=0000=/1, PLL1SRC=MSI 4MHz
mww [expr {0x46020C28 + $offset}] 0x00000001
# RCC_PLL1CFGR => PLL1MBOOST=0, PLL1M=0=/1, PLL1FRACEN=0, PLL1SRC=MSI 4MHz
# PLL1REN=1, PLL1RGE => VCOInputRange=PLLInputRange_4_8
mww [expr {0x46020C28 + $offset}] 0x00040009
# Enable EPOD Booster
mmw [expr {0x4602080C + $offset}] 0x00040000 0
# while !(PWR_VOSR & BOOSTRDY)
while {!([mrw [expr {0x4602080C + $offset}]] & 0x00004000)} {}
# RCC_PLL1DIVR => PLL1P=PLL1Q=PLL1R=000001=/2, PLL1N=0x4F=80
# fVCO = 4 x 80 /1 = 320
# SYSCLOCK = fVCO/PLL1R = 320/2 = 160 MHz
mmw [expr {0x46020C34 + $offset}] 0x0000004F 0
# RCC_PLL1CFGR => PLL1REN=1
mmw [expr {0x46020C28 + $offset}] 0x00040000 0
mww [expr {0x46020C34 + $offset}] 0x0101024F
# RCC_CR |= PLL1ON
mmw [expr {0x46020C00 + $offset}] 0x01000000 0
# while !(RCC_CR & PLL1RDY)