tcl/xtensa: some fixes at xtensa-core-esp32s3.cfg
Some config changes required to run ESP32-S3 with full feature set Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I38022bb5ff5830e1cf9d11d6fe795ea99d91e9db Reviewed-on: https://review.openocd.org/c/openocd/+/7254 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Erhan Kurubas
Antonio Borneo
parent
48317d86d3
commit
45c9e1e8c0
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@ -20,6 +20,7 @@ xtensa xtmem irom 0x40000000 0x60000
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xtensa xtmem iram 0x40370000 0x70000
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xtensa xtmem iram 0x600FE000 0x2000
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xtensa xtmem drom 0x3C000000 0x1000000
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xtensa xtmem drom 0x3FF00000 0x20000
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xtensa xtmem dram 0x3FC88000 0x78000
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xtensa xtmem dram 0x600FE000 0x2000
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xtensa xtmem dram 0x50000000 0x2000
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@ -31,8 +32,8 @@ xtensa xtmem dram 0x60000000 0x10000000
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xtensa xtopt debuglevel 6
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xtensa xtopt ibreaknum 2
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xtensa xtopt dbreaknum 2
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xtensa xtopt tracemem 16384
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xtensa xtopt tracememrev 1
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xtensa xtopt tracemem 0x4000
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xtensa xtopt tracememrev 0
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xtensa xtopt perfcount 2
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@ -43,7 +44,7 @@ xtensa xtopt perfcount 2
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# in "Read General Registers" (g-packet) requests.
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# NOTE: For contiguous format, registers listed in GDB order.
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# xtregs: Total number of Xtensa registers in the system
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xtensa xtregs 244
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xtensa xtregs 228
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xtensa xtregfmt contiguous 128
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xtensa xtreg pc 0x0020
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xtensa xtreg ar0 0x0100
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@ -128,10 +129,7 @@ xtensa xtreg m0 0x0220
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xtensa xtreg m1 0x0221
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xtensa xtreg m2 0x0222
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xtensa xtreg m3 0x0223
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# TODO: update gpioout address while testing on S3 HW
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xtensa xtreg gpioout 0x02f4
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xtensa xtreg gpio_out 0x030c
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xtensa xtreg f0 0x0030
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xtensa xtreg f1 0x0031
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xtensa xtreg f2 0x0032
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@ -150,35 +148,32 @@ xtensa xtreg f14 0x003e
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xtensa xtreg f15 0x003f
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xtensa xtreg fcr 0x03e8
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xtensa xtreg fsr 0x03e9
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# TODO: update TIE state
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xtensa xtreg accx_0 0x02f4
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xtensa xtreg accx_1 0x02f4
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xtensa xtreg qacc_h_0 0x02f4
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xtensa xtreg qacc_h_1 0x02f4
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xtensa xtreg qacc_h_2 0x02f4
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xtensa xtreg qacc_h_3 0x02f4
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xtensa xtreg qacc_h_4 0x02f4
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xtensa xtreg qacc_l_0 0x02f4
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xtensa xtreg qacc_l_1 0x02f4
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xtensa xtreg qacc_l_2 0x02f4
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xtensa xtreg qacc_l_3 0x02f4
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xtensa xtreg qacc_l_4 0x02f4
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xtensa xtreg sar_byte 0x02f4
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xtensa xtreg fft_bit_width 0x02f4
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xtensa xtreg ua_state_0 0x02f4
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xtensa xtreg ua_state_1 0x02f4
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xtensa xtreg ua_state_2 0x02f4
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xtensa xtreg ua_state_3 0x02f4
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xtensa xtreg q0 0x02f4
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xtensa xtreg q1 0x02f4
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xtensa xtreg q2 0x02f4
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xtensa xtreg q3 0x02f4
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xtensa xtreg q4 0x02f4
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xtensa xtreg q5 0x02f4
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xtensa xtreg q6 0x02f4
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xtensa xtreg q7 0x02f4
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xtensa xtreg accx_0 0x0300
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xtensa xtreg accx_1 0x0301
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xtensa xtreg qacc_h_0 0x0302
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xtensa xtreg qacc_h_1 0x0303
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xtensa xtreg qacc_h_2 0x0304
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xtensa xtreg qacc_h_3 0x0305
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xtensa xtreg qacc_h_4 0x0306
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xtensa xtreg qacc_l_0 0x0307
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xtensa xtreg qacc_l_1 0x0308
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xtensa xtreg qacc_l_2 0x0309
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xtensa xtreg qacc_l_3 0x030a
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xtensa xtreg qacc_l_4 0x030b
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xtensa xtreg sar_byte 0x030d
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xtensa xtreg fft_bit_width 0x030e
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xtensa xtreg ua_state_0 0x030f
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xtensa xtreg ua_state_1 0x0310
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xtensa xtreg ua_state_2 0x0311
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xtensa xtreg ua_state_3 0x0312
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xtensa xtreg q0 0x1008
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xtensa xtreg q1 0x1009
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xtensa xtreg q2 0x100a
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xtensa xtreg q3 0x100b
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xtensa xtreg q4 0x100c
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xtensa xtreg q5 0x100d
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xtensa xtreg q6 0x100e
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xtensa xtreg q7 0x100f
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xtensa xtreg mmid 0x0259
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xtensa xtreg ibreakenable 0x0260
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xtensa xtreg memctl 0x0261
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@ -231,38 +226,38 @@ xtensa xtreg misc0 0x02f4
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xtensa xtreg misc1 0x02f5
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xtensa xtreg misc2 0x02f6
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xtensa xtreg misc3 0x02f7
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xtensa xtreg pwrctl 0x2025
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xtensa xtreg pwrstat 0x2026
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xtensa xtreg eristat 0x2027
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xtensa xtreg cs_itctrl 0x2028
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xtensa xtreg cs_claimset 0x2029
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xtensa xtreg cs_claimclr 0x202a
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xtensa xtreg cs_lockaccess 0x202b
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xtensa xtreg cs_lockstatus 0x202c
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xtensa xtreg cs_authstatus 0x202d
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xtensa xtreg fault_info 0x203c
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xtensa xtreg trax_id 0x203d
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xtensa xtreg trax_control 0x203e
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xtensa xtreg trax_status 0x203f
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xtensa xtreg trax_data 0x2040
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xtensa xtreg trax_address 0x2041
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xtensa xtreg trax_pctrigger 0x2042
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xtensa xtreg trax_pcmatch 0x2043
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xtensa xtreg trax_delay 0x2044
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xtensa xtreg trax_memstart 0x2045
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xtensa xtreg trax_memend 0x2046
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xtensa xtreg pmg 0x2054
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xtensa xtreg pmpc 0x2055
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xtensa xtreg pm0 0x2056
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xtensa xtreg pm1 0x2057
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xtensa xtreg pmctrl0 0x2058
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xtensa xtreg pmctrl1 0x2059
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xtensa xtreg pmstat0 0x205a
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xtensa xtreg pmstat1 0x205b
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xtensa xtreg ocdid 0x205c
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xtensa xtreg ocd_dcrclr 0x205d
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xtensa xtreg ocd_dcrset 0x205e
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xtensa xtreg ocd_dsr 0x205f
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xtensa xtreg pwrctl 0x2028
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xtensa xtreg pwrstat 0x2029
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xtensa xtreg eristat 0x202a
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xtensa xtreg cs_itctrl 0x202b
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xtensa xtreg cs_claimset 0x202c
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xtensa xtreg cs_claimclr 0x202d
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xtensa xtreg cs_lockaccess 0x202e
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xtensa xtreg cs_lockstatus 0x202f
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xtensa xtreg cs_authstatus 0x2030
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xtensa xtreg fault_info 0x203f
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xtensa xtreg trax_id 0x2040
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xtensa xtreg trax_control 0x2041
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xtensa xtreg trax_status 0x2042
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xtensa xtreg trax_data 0x2043
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xtensa xtreg trax_address 0x2044
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xtensa xtreg trax_pctrigger 0x2045
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xtensa xtreg trax_pcmatch 0x2046
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xtensa xtreg trax_delay 0x2047
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xtensa xtreg trax_memstart 0x2048
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xtensa xtreg trax_memend 0x2049
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xtensa xtreg pmg 0x2057
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xtensa xtreg pmpc 0x2058
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xtensa xtreg pm0 0x2059
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xtensa xtreg pm1 0x205a
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xtensa xtreg pmctrl0 0x205b
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xtensa xtreg pmctrl1 0x205c
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xtensa xtreg pmstat0 0x205d
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xtensa xtreg pmstat1 0x205e
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xtensa xtreg ocdid 0x205f
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xtensa xtreg ocd_dcrclr 0x2060
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xtensa xtreg ocd_dcrset 0x2061
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xtensa xtreg ocd_dsr 0x2062
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xtensa xtreg a0 0x0000
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xtensa xtreg a1 0x0001
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xtensa xtreg a2 0x0002
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@ -279,19 +274,3 @@ xtensa xtreg a12 0x000c
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xtensa xtreg a13 0x000d
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xtensa xtreg a14 0x000e
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xtensa xtreg a15 0x000f
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xtensa xtreg b0 0x0010
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xtensa xtreg b1 0x0011
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xtensa xtreg b2 0x0012
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xtensa xtreg b3 0x0013
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xtensa xtreg b4 0x0014
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xtensa xtreg b5 0x0015
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xtensa xtreg b6 0x0016
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xtensa xtreg b7 0x0017
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xtensa xtreg b8 0x0018
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xtensa xtreg b9 0x0019
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xtensa xtreg b10 0x001a
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xtensa xtreg b11 0x001b
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xtensa xtreg b12 0x001c
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xtensa xtreg b13 0x001d
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xtensa xtreg b14 0x001e
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xtensa xtreg b15 0x001f
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