tcl/xtensa: some fixes at xtensa-core-esp32s2.cfg
Some config changes required to run ESP32-S2 with full feature set Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: Ie0a742442254ec6e95d4e05be40213b079a94dab Reviewed-on: https://review.openocd.org/c/openocd/+/7253 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Erhan Kurubas
Antonio Borneo
parent
46a61ea7ab
commit
48317d86d3
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@ -23,6 +23,7 @@ xtensa xtmem iram 0x40020000 0x50000
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xtensa xtmem iram 0x40070000 0x2000
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xtensa xtmem drom 0x3F000000 0x400000
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xtensa xtmem drom 0x3F4D3FFC 0xAAC004
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xtensa xtmem drom 0x3FFA0000 0x10000
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xtensa xtmem dram 0x3FFB0000 0x50000
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xtensa xtmem dram 0x3FF9E000 0x2000
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xtensa xtmem dram 0x50000000 0x2000
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@ -36,8 +37,8 @@ xtensa xtmem dram 0x60000000 0x20000000
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xtensa xtopt debuglevel 6
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xtensa xtopt ibreaknum 2
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xtensa xtopt dbreaknum 2
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xtensa xtopt tracemem 8192
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xtensa xtopt tracememrev 1
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xtensa xtopt tracemem 0x4000
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xtensa xtopt tracememrev 0
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xtensa xtopt perfcount 2
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# Core Registers
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@ -48,7 +49,7 @@ xtensa xtopt perfcount 2
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# NOTE: For contiguous format, registers listed in GDB order.
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# xtregs: Total number of Xtensa registers in the system
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xtensa xtregs 171
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xtensa xtregfmt contiguous 72
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xtensa xtregfmt contiguous 73
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xtensa xtreg pc 0x0020
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xtensa xtreg ar0 0x0100
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xtensa xtreg ar1 0x0101
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@ -121,8 +122,7 @@ xtensa xtreg configid0 0x02b0
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xtensa xtreg configid1 0x02d0
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xtensa xtreg ps 0x02e6
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xtensa xtreg threadptr 0x03e7
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# gpio_out should be 0x0300? Hits an exception on wrover
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xtensa xtreg gpio_out 0x0268
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xtensa xtreg gpio_out 0x0300
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xtensa xtreg mmid 0x0259
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xtensa xtreg ibreakenable 0x0260
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xtensa xtreg ddr 0x0268
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@ -173,6 +173,38 @@ xtensa xtreg misc0 0x02f4
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xtensa xtreg misc1 0x02f5
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xtensa xtreg misc2 0x02f6
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xtensa xtreg misc3 0x02f7
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xtensa xtreg pwrctl 0x2014
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xtensa xtreg pwrstat 0x2015
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xtensa xtreg eristat 0x2016
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xtensa xtreg cs_itctrl 0x2017
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xtensa xtreg cs_claimset 0x2018
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xtensa xtreg cs_claimclr 0x2019
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xtensa xtreg cs_lockaccess 0x201a
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xtensa xtreg cs_lockstatus 0x201b
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xtensa xtreg cs_authstatus 0x201c
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xtensa xtreg fault_info 0x202b
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xtensa xtreg trax_id 0x202c
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xtensa xtreg trax_control 0x202d
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xtensa xtreg trax_status 0x202e
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xtensa xtreg trax_data 0x202f
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xtensa xtreg trax_address 0x2030
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xtensa xtreg trax_pctrigger 0x2031
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xtensa xtreg trax_pcmatch 0x2032
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xtensa xtreg trax_delay 0x2033
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xtensa xtreg trax_memstart 0x2034
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xtensa xtreg trax_memend 0x2035
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xtensa xtreg pmg 0x2043
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xtensa xtreg pmpc 0x2044
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xtensa xtreg pm0 0x2045
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xtensa xtreg pm1 0x2046
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xtensa xtreg pmctrl0 0x2047
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xtensa xtreg pmctrl1 0x2048
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xtensa xtreg pmstat0 0x2049
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xtensa xtreg pmstat1 0x204a
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xtensa xtreg ocdid 0x204b
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xtensa xtreg ocd_dcrclr 0x204c
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xtensa xtreg ocd_dcrset 0x204d
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xtensa xtreg ocd_dsr 0x204e
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xtensa xtreg a0 0x0000
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xtensa xtreg a1 0x0001
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xtensa xtreg a2 0x0002
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@ -189,35 +221,3 @@ xtensa xtreg a12 0x000c
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xtensa xtreg a13 0x000d
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xtensa xtreg a14 0x000e
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xtensa xtreg a15 0x000f
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xtensa xtreg pwrctl 0x2028
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xtensa xtreg pwrstat 0x2029
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xtensa xtreg eristat 0x202a
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xtensa xtreg cs_itctrl 0x202b
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xtensa xtreg cs_claimset 0x202c
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xtensa xtreg cs_claimclr 0x202d
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xtensa xtreg cs_lockaccess 0x202e
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xtensa xtreg cs_lockstatus 0x202f
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xtensa xtreg cs_authstatus 0x2030
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xtensa xtreg fault_info 0x203f
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xtensa xtreg trax_id 0x2040
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xtensa xtreg trax_control 0x2041
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xtensa xtreg trax_status 0x2042
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xtensa xtreg trax_data 0x2043
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xtensa xtreg trax_address 0x2044
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xtensa xtreg trax_pctrigger 0x2045
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xtensa xtreg trax_pcmatch 0x2046
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xtensa xtreg trax_delay 0x2047
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xtensa xtreg trax_memstart 0x2048
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xtensa xtreg trax_memend 0x2049
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xtensa xtreg pmg 0x2057
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xtensa xtreg pmpc 0x2058
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xtensa xtreg pm0 0x2059
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xtensa xtreg pm1 0x205a
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xtensa xtreg pmctrl0 0x2061
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xtensa xtreg pmctrl1 0x2062
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xtensa xtreg pmstat0 0x2069
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xtensa xtreg pmstat1 0x206a
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xtensa xtreg ocdid 0x2071
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xtensa xtreg ocd_dcrclr 0x2072
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xtensa xtreg ocd_dcrset 0x2073
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xtensa xtreg ocd_dsr 0x2074
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