target/board: Add Ampere QS|MQ config files
Add Ampere Altra ("Quicksilver") and Ampere Altra Max ("Mystique")
target/board configuration files.
The target configuration file supports silicon and emulation.
The board configuration files support 1 and 2 socket platforms.
Tested on Ampere emulation and silicon
Change-Id: I036c798a50624e30ab51ccd2895b6f60c40be096
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5591
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This commit is contained in:
Daniel Goehring
Antonio Borneo
parent
c28ae626a2
commit
52fbb85d2e
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@ -0,0 +1,100 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
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# Ampere Altra Max ("Mystique") processors
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#
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# Copyright (c) 2019-2021, Ampere Computing LLC
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# Argument Description
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#
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# JTAGFREQ
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# Set the JTAG clock frequency
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# Syntax: -c "set JTAGFREQ {freq_in_khz}"
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#
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# SYSNAME
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# Set the system name
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# If not specified, defaults to "qs"
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# Syntax: -c "set SYSNAME {qs}"
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#
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# Life-Cycle State (LCS)
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# If not specified, defaults to "Secure LCS"
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# LCS=0, "Secure LCS"
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# LCS=1, "Chip Manufacturing LCS"
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# Syntax: -c "set LCS {0}"
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# Syntax: -c "set LCS {1}"
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#
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# CORELIST_S0
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# Specify available physical cores by number
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# Example syntax to connect to physical cores 16 and 17 for S0
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# Syntax: -c "set CORELIST_S0 {16 17}"
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#
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# COREMASK_S0_LO
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# Specify available physical cores 0-63 by mask
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# Example syntax to connect to physical cores 16 and 17 for S0
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# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
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#
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# COREMASK_S0_HI
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# Specify available physical cores 64 and above by mask
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# Example syntax to connect to physical cores 94 and 95 for S0
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# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
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#
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# PHYS_IDX
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# Enable OpenOCD ARMv8 core target physical indexing
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# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
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# Syntax: -c "set PHYS_IDX {}"
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#
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# Configure JTAG speed
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#
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if { [info exists JTAGFREQ] } {
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adapter speed $JTAGFREQ
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} else {
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adapter speed 100
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}
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#
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# Set the system name
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#
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if { [info exists SYSNAME] } {
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set _SYSNAME $SYSNAME
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} else {
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set _SYSNAME qs
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}
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#
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# Configure Resets
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#
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jtag_ntrst_delay 100
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reset_config trst_only
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#
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# Configure Targets
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#
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if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] } {
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set CHIPNAME ${_SYSNAME}0
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if { [info exists CORELIST_S0] } {
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set CORELIST $CORELIST_S0
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} else {
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if { [info exists COREMASK_S0_LO] } {
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set COREMASK_LO $COREMASK_S0_LO
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} else {
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set COREMASK_LO 0x0
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}
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if { [info exists COREMASK_S0_HI] } {
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set COREMASK_HI $COREMASK_S0_HI
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} else {
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set COREMASK_HI 0x0
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}
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}
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} else {
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set CHIPNAME ${_SYSNAME}0
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set COREMASK_LO 0x1
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set COREMASK_HI 0x0
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}
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source [find target/ampere_qs_mq.cfg]
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@ -0,0 +1,164 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
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# Ampere Altra Max ("Mystique") processors
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#
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# Copyright (c) 2019-2021, Ampere Computing LLC
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# Argument Description
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#
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# JTAGFREQ
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# Set the JTAG clock frequency
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# Syntax: -c "set JTAGFREQ {freq_in_khz}"
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#
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# SYSNAME
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# Set the system name
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# If not specified, defaults to "qs"
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# Syntax: -c "set SYSNAME {qs}"
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#
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# Life-Cycle State (LCS)
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# If not specified, defaults to "Secure LCS"
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# LCS=0, "Secure LCS"
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# LCS=1, "Chip Manufacturing LCS"
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# Syntax: -c "set LCS {0}"
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# Syntax: -c "set LCS {1}"
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#
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# CORELIST_S0, CORELIST_S1
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# Specify available physical cores by number
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# Example syntax to connect to physical cores 16 and 17 for S0 and S1
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# Syntax: -c "set CORELIST_S0 {16 17}"
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# Syntax: -c "set CORELIST_S1 {16 17}"
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#
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# COREMASK_S0_LO, COREMASK_S1_LO
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# Specify available physical cores 0-63 by mask
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# Example syntax to connect to physical cores 16 and 17 for S0 and S1
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# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
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# Syntax: -c "set COREMASK_S1_LO {0x0000000000030000}"
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#
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# COREMASK_S0_HI, COREMASK_S1_HI
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# Specify available physical cores 64 and above by mask
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# Example syntax to connect to physical cores 94 and 95 for S0 and S1
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# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
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# Syntax: -c "set COREMASK_S1_HI {0x00000000C0000000}"
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#
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# SPLITSMP
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# Group all ARMv8 cores per socket into individual SMP sessions
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# If not specified, group ARMv8 cores from both sockets into one SMP session
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# Syntax: -c "set SPLITSMP {}"
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#
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# PHYS_IDX
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# Enable OpenOCD ARMv8 core target physical indexing
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# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
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# Syntax: -c "set PHYS_IDX {}"
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#
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# Configure JTAG speed
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#
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if { [info exists JTAGFREQ] } {
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adapter speed $JTAGFREQ
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} else {
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adapter speed 100
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}
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#
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# Set the system name
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#
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if { [info exists SYSNAME] } {
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set _SYSNAME $SYSNAME
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} else {
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set _SYSNAME qs
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}
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#
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# Configure Board level SMP configuration if necessary
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#
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if { ![info exists SPLITSMP] } {
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# Group dual chip into a single SMP configuration
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set SMP_STR "target smp"
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set CORE_INDEX_OFFSET 0
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set DUAL_SOCKET_SMP_ENABLED ""
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}
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#
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# Configure Resets
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#
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jtag_ntrst_delay 100
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reset_config trst_only
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#
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# Configure Targets
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#
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if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] || \
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[info exists CORELIST_S1] || [info exists COREMASK_S1_LO] || [info exists COREMASK_S1_HI] } {
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set CHIPNAME ${_SYSNAME}1
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if { [info exists CORELIST_S1] } {
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set CORELIST $CORELIST_S1
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} else {
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if { [info exists COREMASK_S1_LO] } {
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set COREMASK_LO $COREMASK_S1_LO
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} else {
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set COREMASK_LO 0x0
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}
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if { [info exists COREMASK_S1_HI] } {
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set COREMASK_HI $COREMASK_S1_HI
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} else {
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set COREMASK_HI 0x0
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}
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}
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source [find target/ampere_qs_mq.cfg]
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if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
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if { [info exists MQ_ENABLE] } {
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set CORE_INDEX_OFFSET 128
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} else {
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set CORE_INDEX_OFFSET 80
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}
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}
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set CHIPNAME ${_SYSNAME}0
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if { [info exists CORELIST_S0] } {
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set CORELIST $CORELIST_S0
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} else {
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if { [info exists COREMASK_S0_LO] } {
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set COREMASK_LO $COREMASK_S0_LO
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} else {
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set COREMASK_LO 0x0
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}
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if { [info exists COREMASK_S0_HI] } {
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set COREMASK_HI $COREMASK_S0_HI
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} else {
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set COREMASK_HI 0x0
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}
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}
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source [find target/ampere_qs_mq.cfg]
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} else {
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set CHIPNAME ${_SYSNAME}1
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set COREMASK_LO 0x0
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set COREMASK_HI 0x0
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source [find target/ampere_qs_mq.cfg]
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if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
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if { [info exists MQ_ENABLE] } {
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set CORE_INDEX_OFFSET 128
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} else {
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set CORE_INDEX_OFFSET 80
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}
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}
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set CHIPNAME ${_SYSNAME}0
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set COREMASK_LO 0x1
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set COREMASK_HI 0x0
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source [find target/ampere_qs_mq.cfg]
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}
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if { [info exists DUAL_SOCKET_SMP_ENABLED] } {
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# For dual socket SMP configuration, evaluate the string
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eval $SMP_STR
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}
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@ -0,0 +1,333 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# OpenOCD Target Configuration for Ampere Altra ("Quicksilver") and
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# Ampere Altra Max ("Mystique") processors
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#
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# Copyright (c) 2019-2022, Ampere Computing LLC
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# Command Line Argument Description
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#
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# SPLITSMP
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# Only used for dual socket systems. Do not use for a single socket setup.
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# Option pertains to the ARMv8 target core naming in a dual socket setup.
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# If specified, name all ARMv8 cores per socket as individual SMP sessions.
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# If not specified, name ARMv8 cores from both sockets as one SMP session.
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# This option is used in conjunction with the SMP_STR board file option.
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# Syntax: -c "set SPLITSMP {}"
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#
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# PHYS_IDX
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# Enable OpenOCD ARMv8 core target physical indexing.
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# If not specified, defaults to OpenOCD ARMv8 core target logical indexing.
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# Syntax: -c "set PHYS_IDX {}"
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#
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# CHIPNAME
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# Specifies the name of the chip.
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# Will typically be either qs, qs0, qs1, mq, mq0 or mq1.
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# If not specified, defaults to qs.
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# Syntax: -c "set CHIPNAME {qs}"
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#
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# SYSNAME
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# Specifies the name of the system.
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# Will typically be either qs or mq.
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# If not specified, defaults to qs.
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# Syntax: -c "set SYSNAME {qs}"
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#
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# Life-Cycle State (LCS)
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# If not specified, defaults to "Secure LCS".
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# LCS=0, "Secure LCS"
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# LCS=1, "Chip Manufacturing LCS"
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# Syntax: -c "set LCS {0}"
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# Syntax: -c "set LCS {1}"
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#
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# CORELIST
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# Specify available physical cores by number.
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# Example syntax to connect to physical cores 16 and 17.
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# Syntax: -c "set CORELIST {16 17}"
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#
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# COREMASK_LO
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# Specify available physical cores 0-63 by mask.
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# Example syntax to connect to physical cores 16 and 17.
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# Syntax: -c "set COREMASK_LO {0x0000000000030000}"
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#
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# COREMASK_HI
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# Specify available physical cores 64 and above by mask.
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# Example syntax to connect to physical cores 94 and 95.
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# Syntax: -c "set COREMASK_HI {0x00000000C0000000}"
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#
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# ARMV8_TAPID
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# Can override the ARMV8 TAPID default value if necessary.
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# Experimental Use. Most users will not use this option.
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# Syntax: -c "set ARMV8_TAPID {0x3BA06477}"
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#
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# SMPMPRO_TAPID
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# Can override the SMPMPRO TAPID default value if necessary.
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# Experimental Use. Most users will not use this option.
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# Syntax: -c "set SMPMPRO_TAPID {0x4BA00477}"
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#
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#
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# Board File Argument Description
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# These optional arguments are defined in the board file and
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# referenced by the target file. See the corresponding board
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# files for examples of their use.
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#
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# SMP_STR
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# This option is used primarily for a dual socket system and it is not
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# recommended for a single socket setup. This option configures whether
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# the SMP ARMv8 core grouping is maintained at the board or target cfg level.
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# Specify the option if the SMP core grouping is defined at the board level.
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# Do not specify if the SMP core grouping is defined at the chip level.
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# If not specified, defaults to SMP core grouping defined per socket.
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# If specified, "SMP_STR=target smp", the SMP core grouping is maintained
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# at the board cfg level.
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# Used in conjunction with the SPLITSMP option to group two chips into
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# a single SMP configuration or maintain as two separate SMP sessions.
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#
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# CORE_INDEX_OFFSET
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# Specifies the starting logical core index value.
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# Used for dual-socket systems.
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# For socket #0, set to 0.
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# For socket #1, set the starting logical core based from
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# the last logical core on socket #0.
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# If not specified, defaults to 0.
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#
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#
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# Configure defaults for target.
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# Can be overridden in board configuration file.
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#
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if { [info exists SMP_STR] } {
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# SMP configured at the dual socket board level
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set _SMP_STR $SMP_STR
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} else {
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# SMP configured at the single socket target level
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set _SMP_STR "target smp"
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}
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME qs
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}
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if { [info exists SYSNAME] } {
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set _SYSNAME $SYSNAME
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} else {
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set _SYSNAME qs
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}
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if { [info exists CORE_INDEX_OFFSET] } {
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set _CORE_INDEX_OFFSET $CORE_INDEX_OFFSET
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} else {
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set _CORE_INDEX_OFFSET 0
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists ARMV8_TAPID] } {
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set _ARMV8_TAPID $ARMV8_TAPID
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} else {
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if { [info exists MQ_ENABLE] } {
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# Configure for Mystique
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set _ARMV8_TAPID 0x3BA06477
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set _MAX_CORE 128
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} else {
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# Configure for Quicksilver
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set _ARMV8_TAPID 0x2BA06477
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set _MAX_CORE 80
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}
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}
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if { [info exists SMPMPRO_TAPID] } {
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set _SMPMPRO_TAPID $SMPMPRO_TAPID
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} else {
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set _SMPMPRO_TAPID 0x4BA00477
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}
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if { [info exists CORELIST] } {
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set _CORELIST $CORELIST
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} else {
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if { [info exists COREMASK_LO] } {
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set _COREMASK_LO $COREMASK_LO
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} else {
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set _COREMASK_LO 0x0
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}
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if { [info exists COREMASK_HI] } {
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set _COREMASK_HI $COREMASK_HI
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} else {
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set _COREMASK_HI 0x0
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}
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set _CORELIST {}
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set _MASK 0x1
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for {set i 0} {$i < 64} {incr i} {
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if { [expr {$_COREMASK_LO & $_MASK}] != 0x0 } {
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set _CORELIST "$_CORELIST $i"
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}
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set _MASK [expr {$_MASK << 0x1}]
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}
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set _MASK 0x1
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for {} {$i < $_MAX_CORE} {incr i} {
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if { [expr {$_COREMASK_HI & $_MASK}] != 0x0 } {
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set _CORELIST "$_CORELIST $i"
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}
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set _MASK [expr {$_MASK << 0x1}]
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}
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}
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#
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# Definition of target names
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#
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set _TARGETNAME_PMPRO pmpro
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set _TARGETNAME_SMPRO smpro
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set _TARGETNAME_ARMV8 armv8
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#
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# Configure JTAG TAPs - TAP chain declaration order is important
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#
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jtag newtap $_CHIPNAME pmpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID
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set _TAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.tap
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|
||||
jtag newtap $_CHIPNAME smpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID
|
||||
set _TAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.tap
|
||||
|
||||
jtag newtap $_CHIPNAME armv8.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_ARMV8_TAPID
|
||||
set _TAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.tap
|
||||
|
||||
set _DAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.dap
|
||||
set _DAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.dap
|
||||
set _DAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.dap
|
||||
|
||||
set _AP_PMPRO_AHB 0
|
||||
set _AP_SMPRO_AHB 0
|
||||
set _AP_ARMV8_APB 0x00010000
|
||||
set _AP_ARMV8_AXI 0x00020000
|
||||
|
||||
#
|
||||
# Configure JTAG DAPs
|
||||
#
|
||||
|
||||
dap create $_DAPNAME_PMPRO -chain-position $_TAPNAME_PMPRO -adiv5
|
||||
dap create $_DAPNAME_SMPRO -chain-position $_TAPNAME_SMPRO -adiv5
|
||||
dap create $_DAPNAME_ARMV8 -chain-position $_TAPNAME_ARMV8 -adiv6
|
||||
|
||||
if { [info exists LCS] && [expr {"$LCS"!="0"}] } {
|
||||
#
|
||||
# Create the DAP AHB-AP MEM-AP target for the PMPRO CPU
|
||||
#
|
||||
|
||||
target create $_CHIPNAME.$_TARGETNAME_PMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB
|
||||
|
||||
#
|
||||
# Configure target PMPRO CPU
|
||||
#
|
||||
|
||||
target create $_CHIPNAME.$_TARGETNAME_PMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB
|
||||
|
||||
#
|
||||
# Create the DAP AHB-AP MEM-AP target for the SMPRO CPU
|
||||
#
|
||||
|
||||
target create $_CHIPNAME.$_TARGETNAME_SMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB
|
||||
|
||||
#
|
||||
# Configure target SMPRO CPU
|
||||
#
|
||||
|
||||
target create $_CHIPNAME.$_TARGETNAME_SMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB
|
||||
}
|
||||
|
||||
# Create the DAP APB-AP MEM-AP target for the ARMV8 cores
|
||||
target create $_CHIPNAME.$_TARGETNAME_ARMV8.apb mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB
|
||||
|
||||
# Create the DAP AXI-AP MEM-AP target for the ARMV8 cores
|
||||
target create $_CHIPNAME.$_TARGETNAME_ARMV8.axi mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_AXI
|
||||
|
||||
# Set CSW register value default correctly for AXI accessible device memory:
|
||||
# Select the correct Access Port Number
|
||||
$_DAPNAME_ARMV8 apsel $_AP_ARMV8_AXI
|
||||
# First set the CSW to OpenOCD's internal default
|
||||
$_DAPNAME_ARMV8 apcsw default
|
||||
# Set Domain[1:0]=b'11 (CSW[14:13]=b'11)
|
||||
# Set Cache[3:0]=b'0000 (CSW[27:24]=b'0000)
|
||||
# Porter Cfg registers require secure access, AxPROT[1] (CSW[29]) must be b'0'.
|
||||
# Set AxPROT[2:0]=b'000 (CSW[30:28]=b'000) for an Unpriveleged, Secure, Data access.
|
||||
$_DAPNAME_ARMV8 apcsw 0x00006000 0x7F006000
|
||||
|
||||
#
|
||||
# Configure target CPUs
|
||||
#
|
||||
|
||||
set logical_index $_CORE_INDEX_OFFSET
|
||||
|
||||
foreach physical_index $_CORELIST {
|
||||
if { [info exists PHYS_IDX] } {
|
||||
set logical_index [expr {$physical_index + $_CORE_INDEX_OFFSET}]
|
||||
}
|
||||
|
||||
# Format a string to reference which CPU target to use
|
||||
if { [info exists SPLITSMP] } {
|
||||
eval "set _TARGETNAME $_CHIPNAME.${_TARGETNAME_ARMV8}_$logical_index"
|
||||
} else {
|
||||
eval "set _TARGETNAME $_SYSNAME.${_TARGETNAME_ARMV8}_$logical_index"
|
||||
}
|
||||
|
||||
# Create and configure Cross Trigger Interface (CTI) - required for halt and resume
|
||||
set _CTINAME $_TARGETNAME.cti
|
||||
set _offset [expr {(0x00100000 * $physical_index) + (0x00200000 * ($physical_index>>1))}]
|
||||
cti create $_CTINAME -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -baseaddr [expr {0xA0220000 + $_offset}]
|
||||
|
||||
# Create the target
|
||||
target create $_TARGETNAME aarch64 -endian $_ENDIAN \
|
||||
-dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -dbgbase [expr {0xA0210000 + $_offset}] \
|
||||
-rtos hwthread -cti $_CTINAME -coreid $logical_index
|
||||
|
||||
# Build string used to enable SMP mode for the ARMv8 CPU cores
|
||||
set _SMP_STR "$_SMP_STR $_TARGETNAME"
|
||||
|
||||
# Clear CTI output/input enables that are not configured by OpenOCD for aarch64
|
||||
$_TARGETNAME configure -event reset-init [subst {
|
||||
$_CTINAME write INEN0 0x00000000
|
||||
$_CTINAME write INEN1 0x00000000
|
||||
$_CTINAME write INEN2 0x00000000
|
||||
$_CTINAME write INEN3 0x00000000
|
||||
$_CTINAME write INEN4 0x00000000
|
||||
$_CTINAME write INEN5 0x00000000
|
||||
$_CTINAME write INEN6 0x00000000
|
||||
$_CTINAME write INEN7 0x00000000
|
||||
$_CTINAME write INEN8 0x00000000
|
||||
|
||||
$_CTINAME write OUTEN0 0x00000000
|
||||
$_CTINAME write OUTEN1 0x00000000
|
||||
$_CTINAME write OUTEN2 0x00000000
|
||||
$_CTINAME write OUTEN3 0x00000000
|
||||
$_CTINAME write OUTEN4 0x00000000
|
||||
$_CTINAME write OUTEN5 0x00000000
|
||||
$_CTINAME write OUTEN6 0x00000000
|
||||
$_CTINAME write OUTEN7 0x00000000
|
||||
$_CTINAME write OUTEN8 0x00000000
|
||||
}]
|
||||
|
||||
incr logical_index
|
||||
}
|
||||
|
||||
if { [info exists SMP_STR] } {
|
||||
# Return updated SMP configuration string back to board level
|
||||
set SMP_STR $_SMP_STR
|
||||
} else {
|
||||
# For single socket per SMP configuration, evaluate the string
|
||||
eval $_SMP_STR
|
||||
}
|
||||
|
||||
if { [info exists CORE_INDEX_OFFSET] } {
|
||||
# For multi-socket, return total number of cores back to board level
|
||||
set CORE_INDEX_OFFSET $logical_index
|
||||
}
|
||||
Loading…
Reference in New Issue