tcl: fix some minor typo
Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. While there, fix one indentation. Change-Id: I72369ed26f363bacd760b40b8c83dd95e89d28a4 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6214 Tested-by: jenkins
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Antonio Borneo
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2a1f3b2574
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@ -2,7 +2,7 @@
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# Purpose - Create some $BIT variables
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# Create $K and $M variables
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# and some bit field extraction variables.
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# Creat helper variables ...
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# Create helper variables ...
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# BIT0.. BIT31
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for { set x 0 } { $x < 32 } { set x [expr {$x + 1}]} {
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@ -5,5 +5,5 @@ source [find target/samsung_s3c4510.cfg]
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#
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# FIXME:
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# Add (A) sdram configuration
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# Add (B) flash cfi programing configuration
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# Add (B) flash cfi programming configuration
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#
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@ -153,7 +153,7 @@ proc at91sam9g20_reset_init { } {
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nand probe nandflash_cs3
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# The AT91SAM9G20-EK evaluation board has build-in serial data flash also.
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# The AT91SAM9G20-EK evaluation board has built-in serial data flash also.
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# Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
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# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference
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@ -5,7 +5,7 @@
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# ID 1443:0007 Digilent Development board JTAG
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#
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# However, the ixo-usb-jtag project provides an alternative open firmware for
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# the on board programmer. When using thie firmware the board will then
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# the on board programmer. When using this firmware the board will then
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# enumerate as:
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# ID 16c0:06ad Van Ooijen Technische Informatica
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# (With SerialNumber == hw_nexys)
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@ -34,7 +34,7 @@ flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
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$_TARGETNAME configure -event reset-init {
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# Flash
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mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not chached
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mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not cached
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# Use PLL
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mww 0xFFFF8020 0x00000001 ;# XTAL_OSC_CONTROL: enable, 1-20 MHz
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@ -38,7 +38,7 @@
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# it's apt-get install libusb-dev. When I made my config I only included
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# --enable-jlink and --enable-usbdevs
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#
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# I HAVE NOT Tested this throughly, so there could still be problems.
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# I HAVE NOT Tested this thoroughly, so there could still be problems.
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# But it should get you way ahead of the game from where I started.
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# If you find problems (and fixes) please post them to
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# openocd-development@lists.berlios.de and join the developers and
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@ -1,5 +1,5 @@
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# Target Configuration for the Uptech 2410 board.
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# This configuration hould also work on smdk2410, but I havn't tested it yet.
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# This configuration should also work on smdk2410, but I haven't tested it yet.
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# Author: xionglingfeng@Gmail.com
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source [find target/samsung_s3c2410.cfg]
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@ -5,7 +5,7 @@
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#
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# You also need to have reliable GND connection between the target and
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# adapter. Vref of the adapter should be supplied with a voltage equal
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# to the target's (preferrably connect it to Vcc). You can also
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# to the target's (preferably connect it to Vcc). You can also
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# optionally connect nSRST. Leave everything else unconnected.
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#
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# FTDI Target
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@ -43,7 +43,7 @@ proc setupTelo {} {
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# setup GPIO used as control signals for C100
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setupGPIO
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# This will allow acces to lower 8MB or NOR
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# This will allow access to lower 8MB or NOR
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lowGPIO5
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# setup NOR size,timing,etc.
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setupNOR
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@ -79,7 +79,7 @@ proc setupNOR {} {
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#mww $EX_CS0_TMG3_REG
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# set EBUS clock 165/5=33MHz
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mww $EX_CLOCK_DIV_REG 0x5
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# everthing else is OK with default
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# everything else is OK with default
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}
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proc bootNOR {} {
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@ -159,7 +159,7 @@ proc boardID {id} {
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proc ooma_board_detect {} {
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set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
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# read the current value of the BOOTSRAP pins
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# read the current value of the BOOTSTRAP pins
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set tmp [mrw $GPIO_BOOTSTRAP_REG]
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echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
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# extract the GPBP bits
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@ -13,16 +13,16 @@ proc helpC100 {} {
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echo "10) showArmClk: will show current config registers for Arm Bus Clock"
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echo "11) setupArmClk: will setup Amba Bus Clock=450MHz"
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echo "12) ooma_board_detect: will show which version of Telo you have"
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echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
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echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configured"
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echo "14) showDDR2: will show DDR2 config registers"
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echo "15) showWatchdog: will show current register config for watchdog"
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echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
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echo "17) bootNOR: will boot Telo from NOR"
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echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
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echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be configured"
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echo "19) putcUART0: will print a character on UART0"
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echo "20) putsUART0: will print a string on UART0"
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echo "21) trainDDR2: will run DDR2 training program"
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echo "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin"
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echo "21) trainDDR2: will run DDR2 training program"
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echo "22) flashUBOOT: will program NOR sectors 0-3 with u-boot.bin"
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}
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source [find mem_helper.tcl]
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@ -267,7 +267,7 @@ proc pll_v03_setup {pll_addr mult config} {
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if {$aln != 0} {
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# clear pllcmd.GO
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mww [expr {$pll_addr + 0x0138}] 0x00
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# write alingment flags
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# write alignment flags
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mww [expr {$pll_addr + 0x0140}] $aln
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# write pllcmd.GO; poll pllstat.GO
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mww [expr {$pll_addr + 0x0138}] 0x01
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@ -56,7 +56,7 @@ proc set_sysclk_500khz {} {
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echo "Notice: sysclock set to 500kHz."
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}
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# Do not remap the ARM interrupt vectors to anything but the beginning ot the flash.
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# Do not remap the ARM interrupt vectors to anything but the beginning of the flash.
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# Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
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# Bit Symbol Value Description
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# 0 map - interrupt vector remap. 0 after boot.
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@ -60,7 +60,7 @@ adapter speed 1500
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#
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# Newer families like PSoC 4000, 4100M, 4200M, 4100L, 4200L and PSoC 4 BLE
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# clear TEST_MODE flag during device reset so workaround is not possible.
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# Use a KitProg adapter for theese devices or "reset halt" will not stop
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# Use a KitProg adapter for these devices or "reset halt" will not stop
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# before executing user code.
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#
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# 3) SWD cannot be connected during system initialization after reset.
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