Eddie Hung
11ac37733d
Add techmap_autopurge to outputs in abc_map.v too
2019-09-23 21:56:28 -07:00
Eddie Hung
27167848f4
Revert "Add a xilinx_finalise pass"
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This reverts commit 23d90e0439
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2019-09-23 19:52:55 -07:00
Eddie Hung
0f53893104
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
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This reverts commit 67c2db3486
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2019-09-23 19:52:55 -07:00
Eddie Hung
29db96fa1f
Revert "Vivado does not like zero width port connections"
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This reverts commit 895e2befa7
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2019-09-23 19:52:54 -07:00
Eddie Hung
895e2befa7
Vivado does not like zero width port connections
2019-09-23 19:04:07 -07:00
Eddie Hung
67c2db3486
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
2019-09-23 18:56:18 -07:00
Eddie Hung
23d90e0439
Add a xilinx_finalise pass
2019-09-23 18:56:02 -07:00
Eddie Hung
e556d48d45
Set [AB]CASCREG to legal values
2019-09-23 16:00:11 -07:00
Eddie Hung
b824a56cde
Comment to explain separating CREG packing
2019-09-23 13:58:10 -07:00
Eddie Hung
15dfbc8125
Separate out CREG packing into new pattern, to avoid conflict with PREG
2019-09-23 13:27:10 -07:00
Eddie Hung
26a6c55665
Move log_debug("\n") later
2019-09-23 13:27:00 -07:00
Eddie Hung
d0dbbc2605
Move unextend initialisation later
2019-09-23 13:26:34 -07:00
Eddie Hung
a67af3d5e5
Use new port() overload once more
2019-09-23 13:00:44 -07:00
Miodrag Milanović
057dae4f78
Merge pull request #1399 from nakengelhardt/fix-show-macos
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fix show command for macos
2019-09-23 20:06:40 +02:00
Eddie Hung
bcee87a457
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-23 10:58:28 -07:00
N. Engelhardt
2b81ce5648
add xdot dependency to Brewfile
2019-09-23 18:25:04 +02:00
N. Engelhardt
3bed4cb18a
fix show command for macos
2019-09-23 17:47:05 +02:00
SergeyDegtyar
1070f2e90b
Add new tests for Efinix architecture.
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Problems/questions:
- fsm.ys. equiv_opt -assert failed because of unproven cells;
- latches.ys,tribuf.ys - internal cells present;
- memory.ys - sat called with -verify and proof did fail.
2019-09-23 15:51:41 +03:00
Benedikt Tutzer
f39269805d
Generate Python wrappers for inline constructors
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Fixes : #1353
2019-09-23 13:17:59 +02:00
Clifford Wolf
0a2d8db793
Merge pull request #1392 from YosysHQ/eddie/fix1391
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(* techmap_autopurge *) fixes when ports aren't consistently-sized
2019-09-21 11:25:36 +02:00
Eddie Hung
7c8de1dd18
Hell let's add the original #1381 testcase too
2019-09-20 17:58:51 -07:00
Eddie Hung
ec08a031b5
Revert abc9.cc
2019-09-20 17:52:23 -07:00
Eddie Hung
6258e6a7e2
Add testcase
2019-09-20 17:51:45 -07:00
Eddie Hung
72ce06909e
Trim mismatched connection to be same (smallest) size
2019-09-20 17:51:36 -07:00
Eddie Hung
567e5f0aa7
Fix first testcase in #1391
2019-09-20 17:51:27 -07:00
Eddie Hung
4401e5f142
Grammar
2019-09-20 14:24:31 -07:00
Eddie Hung
53817b8575
Use new port/param overload in pmg
2019-09-20 14:21:22 -07:00
Eddie Hung
d122083a11
Output pattern matcher items as log_debug()
2019-09-20 12:42:28 -07:00
Eddie Hung
95644b00cb
OPMODE is port not param
2019-09-20 12:37:29 -07:00
Eddie Hung
3fb839e255
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-20 12:21:36 -07:00
Eddie Hung
eb597431f0
Do not run xilinx_dsp_cascadeAB for now
2019-09-20 12:18:37 -07:00
Eddie Hung
0bca366bcd
WIP for xiinx_dsp_cascadeAB
2019-09-20 12:07:14 -07:00
Eddie Hung
b0ad2592be
Run until convergence
2019-09-20 12:04:16 -07:00
Eddie Hung
1b892ca1be
Cleanup ice40_dsp.pmg
2019-09-20 12:03:45 -07:00
Eddie Hung
d88903e610
Cleanup xilinx_dsp
2019-09-20 12:03:25 -07:00
Eddie Hung
1809f463fb
More exceptions
2019-09-20 12:03:10 -07:00
Eddie Hung
ab46d9017b
Fix signedness bug
2019-09-20 10:11:36 -07:00
Eddie Hung
70c5444b25
Update doc
2019-09-20 10:07:54 -07:00
Eddie Hung
ed187ef1cf
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
2019-09-20 10:00:09 -07:00
Eddie Hung
1844498c5f
Add an overload for port/param with default value
2019-09-20 09:59:42 -07:00
Eddie Hung
289cf688b7
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
2019-09-20 09:02:29 -07:00
Eddie Hung
829e4f5d2c
Revert "Move mul2dsp before wreduce"
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This reverts commit e4f4f6a9d5
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2019-09-20 08:56:16 -07:00
Eddie Hung
e4f4f6a9d5
Move mul2dsp before wreduce
2019-09-20 08:41:40 -07:00
Eddie Hung
a0d3ecf8c6
Small cleanup
2019-09-20 08:41:28 -07:00
Clifford Wolf
f3781f98db
Merge pull request #1386 from YosysHQ/clifford/fix1360
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Fix handling of read_verilog config in AstModule::reprocess_module()
2019-09-20 13:30:28 +02:00
Clifford Wolf
8da0888bf6
Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-20 12:16:20 +02:00
Clifford Wolf
c072e00a39
Update CHANGELOG
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-20 10:28:20 +02:00
Clifford Wolf
1f64b34c64
Add "add -mod"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-20 10:27:17 +02:00
Clifford Wolf
db17833a5f
Merge pull request #1384 from YosysHQ/clifford/fix1381
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Add techmap_autopurge attribute
2019-09-20 09:58:42 +02:00
Eddie Hung
8cfcaf108e
Disable support for SB_MAC16 reset since it is async
2019-09-19 22:48:57 -07:00