mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1386 from YosysHQ/clifford/fix1360
Fix handling of read_verilog config in AstModule::reprocess_module()
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commit
f3781f98db
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@ -158,6 +158,11 @@ std::string AST::type2str(AstNodeType type)
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X(AST_POSEDGE)
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X(AST_NEGEDGE)
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X(AST_EDGE)
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X(AST_INTERFACE)
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X(AST_INTERFACEPORT)
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X(AST_INTERFACEPORTTYPE)
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X(AST_MODPORT)
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X(AST_MODPORTMEMBER)
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X(AST_PACKAGE)
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#undef X
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default:
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@ -1291,6 +1296,8 @@ void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule
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// from AST. The interface members are copied into the AST module with the prefix of the interface.
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void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module*> local_interfaces)
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{
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loadconfig();
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bool is_top = false;
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AstNode *new_ast = ast->clone();
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for (auto &intf : local_interfaces) {
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@ -1474,24 +1481,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
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stripped_name = stripped_name.substr(9);
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log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
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current_ast = NULL;
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flag_dump_ast1 = false;
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flag_dump_ast2 = false;
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flag_dump_vlog1 = false;
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flag_dump_vlog2 = false;
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flag_nolatches = nolatches;
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flag_nomeminit = nomeminit;
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flag_nomem2reg = nomem2reg;
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flag_mem2reg = mem2reg;
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flag_noblackbox = noblackbox;
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flag_lib = lib;
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flag_nowb = nowb;
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flag_noopt = noopt;
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flag_icells = icells;
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flag_pwires = pwires;
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flag_autowire = autowire;
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use_internal_line_num();
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loadconfig();
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std::string para_info;
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AstNode *new_ast = ast->clone();
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@ -1572,6 +1562,27 @@ RTLIL::Module *AstModule::clone() const
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return new_mod;
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}
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void AstModule::loadconfig() const
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{
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current_ast = NULL;
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flag_dump_ast1 = false;
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flag_dump_ast2 = false;
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flag_dump_vlog1 = false;
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flag_dump_vlog2 = false;
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flag_nolatches = nolatches;
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flag_nomeminit = nomeminit;
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flag_nomem2reg = nomem2reg;
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flag_mem2reg = mem2reg;
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flag_noblackbox = noblackbox;
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flag_lib = lib;
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flag_nowb = nowb;
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flag_noopt = noopt;
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flag_icells = icells;
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flag_pwires = pwires;
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flag_autowire = autowire;
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use_internal_line_num();
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}
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// internal dummy line number callbacks
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namespace {
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int internal_line_num;
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@ -299,6 +299,7 @@ namespace AST
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std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool mayfail);
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void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE;
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RTLIL::Module *clone() const YS_OVERRIDE;
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void loadconfig() const;
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};
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// this must be set by the language frontend before parsing the sources
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