Miodrag Milanovic
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3e9449cb0b
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make note that it is for latch mode
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2019-09-18 17:48:16 +02:00 |
Miodrag Milanovic
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b0ca6de472
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better lut handling
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2019-09-18 17:45:19 +02:00 |
Miodrag Milanovic
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8badd4d812
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better handling of lut and begin/end add
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2019-09-18 17:45:07 +02:00 |
Clifford Wolf
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779ce3537f
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Add "write_aiger -L"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-18 13:33:02 +02:00 |
Clifford Wolf
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b88d2e5f30
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Fix stupid bug in btor back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-18 11:56:14 +02:00 |
Clifford Wolf
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36df37a734
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Bump version
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-16 13:05:41 +02:00 |
Clifford Wolf
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861f2af5aa
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Merge pull request #1380 from YosysHQ/clifford/fix1372
Fix handling of range selects on loop variables
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2019-09-16 13:05:02 +02:00 |
Clifford Wolf
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25b08b1afd
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Fix handling of range selects on loop variables, fixes #1372
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-16 11:25:37 +02:00 |
Eddie Hung
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2b93b8fc74
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Merge pull request #1374 from YosysHQ/eddie/fix1371
Fix two non-deterministic behaviours that cause divergence between compilers
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2019-09-15 13:56:07 -07:00 |
Marcin Kościelnicki
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09ac36da60
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xilinx: Make blackbox library family-dependent.
Fixes #1246.
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2019-09-15 13:37:24 +02:00 |
Clifford Wolf
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d9f99745da
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Merge pull request #1377 from YosysHQ/clifford/fixzdigit
Fix handling of z_digit "?" and fix optimization of cmp with "z"
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2019-09-15 11:04:31 +02:00 |
Miodrag Milanovic
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3487b95224
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Added simulation models for Efinix and Anlogic
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2019-09-15 09:37:16 +02:00 |
Eddie Hung
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f492567c87
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Oops
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2019-09-13 18:19:07 -07:00 |
Eddie Hung
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681be20ca2
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Add `undef DSP48E1_INST
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2019-09-13 17:07:18 -07:00 |
Eddie Hung
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a2eee9ebef
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Add counter-example from @cliffordwolf
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2019-09-13 16:41:10 -07:00 |
Eddie Hung
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14d72c39c3
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Revert "Make one check $shift(x)? only; change testcase to be 8b"
This reverts commit e2c2d784c8 .
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2019-09-13 16:33:18 -07:00 |
Eddie Hung
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9a84e4711c
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Spacing
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2019-09-13 16:30:44 -07:00 |
Eddie Hung
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9a73adde50
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Explicitly order function arguments
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2019-09-13 16:18:05 -07:00 |
Eddie Hung
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61877e1370
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Fix D -> P{,COUT} delay
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2019-09-13 13:32:55 -07:00 |
Eddie Hung
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d0b202c58d
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Add no MULT no DPORT config
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2019-09-13 12:05:14 -07:00 |
Eddie Hung
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247a63f55d
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Add support for MULT and DPORT
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2019-09-13 11:45:55 -07:00 |
Eddie Hung
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5473e597bf
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Use template specialisation
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2019-09-13 11:13:57 -07:00 |
Eddie Hung
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95e80809a5
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Revert "SigSet<Cell*> to use stable compare class"
This reverts commit 4ea34aaacd .
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2019-09-13 09:49:15 -07:00 |
Eddie Hung
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e235dd0785
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Refine diagram
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2019-09-13 09:34:40 -07:00 |
Clifford Wolf
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a67d63714b
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Fix handling of z_digit "?" and fix optimization of cmp with "z"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-13 13:39:39 +02:00 |
Clifford Wolf
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4da6e19fe1
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Merge pull request #1373 from YosysHQ/clifford/fix1364
Fix lexing of integer literals
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2019-09-13 10:22:34 +02:00 |
Clifford Wolf
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855e6a9b91
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Fix lexing of integer literals without radix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-13 10:19:58 +02:00 |
Eddie Hung
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734034a872
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Add an ASCII drawing
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2019-09-12 18:13:46 -07:00 |
Eddie Hung
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c52863f147
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Finish explanation
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2019-09-12 18:01:49 -07:00 |
Eddie Hung
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aaeaab4ac0
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Rename to techmap_guard
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2019-09-12 17:45:02 -07:00 |
Eddie Hung
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6bb8e6a726
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Initial DSP48E1 box support
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2019-09-12 17:11:01 -07:00 |
Eddie Hung
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3a39073302
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Set more ports explicitly
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2019-09-12 17:10:43 -07:00 |
Eddie Hung
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a1123b095c
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Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-09-12 12:11:11 -07:00 |
Eddie Hung
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c487a8ff25
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Grammar
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2019-09-12 12:00:34 -07:00 |
Eddie Hung
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c05a403dd1
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static_assert to enforce this going forward
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2019-09-12 11:45:17 -07:00 |
Eddie Hung
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4ea34aaacd
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SigSet<Cell*> to use stable compare class
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2019-09-12 11:45:02 -07:00 |
David Shah
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6044fff074
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Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock
Add equiv_opt -multiclock
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2019-09-12 12:26:28 +01:00 |
Clifford Wolf
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7eb593829f
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Fix lexing of integer literals, fixes #1364
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-12 09:43:32 +02:00 |
Eddie Hung
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f3081c20e7
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Add support for A1 and B1 registers
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2019-09-11 17:16:46 -07:00 |
Eddie Hung
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4369fc17d0
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Raise a RuntimeError instead of AssertionError
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2019-09-11 17:06:37 -07:00 |
Eddie Hung
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7d644f40ed
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Add AREG=2 BREG=2 test
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2019-09-11 17:05:47 -07:00 |
Eddie Hung
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6fa6bf483c
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Rename {A,B} -> {A2,B2}
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2019-09-11 16:21:24 -07:00 |
Eddie Hung
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3a49aa6b4a
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Tidy up
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2019-09-11 14:20:49 -07:00 |
Eddie Hung
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817ac7c5e0
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Fix UB
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2019-09-11 14:18:02 -07:00 |
Eddie Hung
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63431fe42a
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Fix UB
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2019-09-11 14:17:45 -07:00 |
Eddie Hung
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690b1a064d
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Add PCOUT -> PCIN non-shifted cascading
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2019-09-11 13:48:45 -07:00 |
Eddie Hung
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c0f26c2da8
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Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
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2019-09-11 13:37:11 -07:00 |
Eddie Hung
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bdb5e0f29c
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Cope with presence of reset muxes too
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2019-09-11 13:36:37 -07:00 |
Eddie Hung
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4937917cd8
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Cleanup
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2019-09-11 13:22:52 -07:00 |
Eddie Hung
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f46ef47893
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Add more tests
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2019-09-11 13:22:41 -07:00 |