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884 Commits

Author SHA1 Message Date
Clifford Wolf 8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
Clifford Wolf 3860c9a9f2 Fixed flatten $meminit handling 2015-07-30 21:43:41 +02:00
Clifford Wolf 4d0ba9b3b2 Fixed "check" command for inout ports 2015-07-27 09:54:58 +02:00
Clifford Wolf 2a613b1b66 Some cleanups in opt_rmdff 2015-07-25 12:09:57 +02:00
Clifford Wolf badc5f7eb9 Added "miter -assert" 2015-07-25 12:09:57 +02:00
Clifford Wolf 2397078485 Keep modules with $assume (like $assert) 2015-07-25 12:09:57 +02:00
Clifford Wolf 914ae3401e Improved $adff simplification 2015-07-24 14:12:50 +02:00
Clifford Wolf ad919ae4e3 Fixed techmap processes error msg 2015-07-18 12:16:27 +02:00
Clifford Wolf 8393f70538 Some fixes in "select" command 2015-07-16 22:10:26 +02:00
Clifford Wolf d2ff5d9994 Do not collect disabled $memwr cells 2015-07-06 13:28:00 +02:00
Clifford Wolf 766dd51447 Bugfix in fsm_extract 2015-07-03 18:42:36 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 053058d781 Added opt_const -clkinv 2015-07-01 10:49:21 +02:00
Clifford Wolf ee9188a5b4 Added logic-loop error handling to freduce 2015-06-30 17:11:46 +02:00
Clifford Wolf 77e89399a6 Bugfix in chparam 2015-06-30 01:38:34 +02:00
Clifford Wolf caa274ada6 Added design->rename(module, new_name) 2015-06-30 01:37:59 +02:00
Clifford Wolf 99100f367d Added "rename -top new_name" 2015-06-17 09:38:56 +02:00
Clifford Wolf 66910e15b2 Modernized memory_dff (and fixed a bug) 2015-06-14 16:15:51 +02:00
Clifford Wolf f6eca509bb Added "memory -nordff" 2015-06-14 15:47:11 +02:00
Clifford Wolf 4c733301e6 Fixed cstr_buf for std::string with small string optimization 2015-06-11 13:39:49 +02:00
Clifford Wolf 1ae360cf72 AigMaker refactoring 2015-06-10 23:00:12 +02:00
Clifford Wolf 56d4822719 Renamed "aig" to "aigmap" 2015-06-10 07:24:26 +02:00
Clifford Wolf 85287295b2 Fixed cellaigs port extending 2015-06-10 07:16:30 +02:00
Clifford Wolf 66f9ee412a Added "aig" pass 2015-06-09 22:33:26 +02:00
Clifford Wolf b57cb4a7fe Merge clock inverters in memory_dff 2015-06-09 07:25:12 +02:00
Clifford Wolf 08f9b38a9c Added opt_share -share_all 2015-05-31 14:24:34 +02:00
Clifford Wolf 522705cc28 Added liberty dont_use support to dfflibmap 2015-05-31 07:51:12 +02:00
Clifford Wolf 9f772eb970 Improved "flatten" handlings of inout ports 2015-05-23 10:14:53 +02:00
Clifford Wolf 4b6221478e Added simple $dlatch support to opt_rmdff 2015-05-23 09:45:48 +02:00
Clifford Wolf e122c2644e preserve used $-wires with init attribute in opt_clean 2015-05-22 08:20:29 +02:00
Clifford Wolf e5116eeb77 Generalized blifparse API 2015-05-17 15:10:37 +02:00
Clifford Wolf 7dad017c9c abc/blifparse files reorganization 2015-05-17 14:44:28 +02:00
Clifford Wolf c2f30e0de4 Added .barbuf support to abc BLIF parser 2015-05-13 06:45:12 +02:00
Clifford Wolf 7462618591 Fixed memory_unpack for initialized memories 2015-04-29 19:55:32 +02:00
Clifford Wolf 96be31de89 Preserve important attributes in splitnets 2015-04-29 07:44:57 +02:00
Clifford Wolf f483dce7c2 Added $eq/$neq -> $logic_not/$reduce_bool optimization 2015-04-29 07:28:15 +02:00
Clifford Wolf 794d22969d Added simplemap $lut support 2015-04-27 10:16:07 +02:00
Clifford Wolf 49859393bb Improved attributes API and handling of "src" attributes 2015-04-24 22:04:05 +02:00
Clifford Wolf 11f77205f5 Fixed memory_share for unconditional write with part select to memory 2015-04-22 06:40:23 +02:00
Clifford Wolf faa95dd845 don't consider blackbox modules in "sat" command 2015-04-18 09:29:03 +02:00
Clifford Wolf 9041f34233 Improved handling of init values in opt_rmdff 
based on a patch by Mingyu Gao, user gaomy3832 on github
 2015-04-18 08:04:31 +02:00
Clifford Wolf 8cdbcf6859 Bugfix for $_DFF_?_ in "dff2dffe -direct-match" 2015-04-17 21:35:59 +02:00
Clifford Wolf e050467b89 Improved "maccmap" help message 2015-04-16 18:23:43 +02:00
Clifford Wolf dc30b034f7 Fixed "dff2dffe -direct-match" 2015-04-16 11:47:59 +02:00
Clifford Wolf f80d020f17 Added "dff2dffe -direct-match" 2015-04-16 11:30:17 +02:00
Clifford Wolf 2fc2f8f5b3 Added "splice -wires" 2015-04-13 19:28:12 +02:00
Clifford Wolf e305d85807 Added handling of bool-output cells to "wreduce" 2015-04-13 19:27:49 +02:00
Clifford Wolf 7319951145 Added memory_bram "make_outreg" feature 2015-04-09 16:08:54 +02:00
Clifford Wolf d176e613c2 Minor fixes in handling of "init" attribute 2015-04-09 15:12:26 +02:00
Clifford Wolf be7b9b34ca techmap code cleanup 2015-04-09 12:02:26 +02:00