Eddie Hung
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57493e328a
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techmap -max_iter to apply to each module individually
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2019-08-20 19:48:16 -07:00 |
Eddie Hung
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c26c556384
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xilinx to use abc_map.v with -max_iter 1
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2019-08-20 19:47:11 -07:00 |
Eddie Hung
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6b1b03d9f7
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ecp5: remove DPR16X4 from abc_unmap.v
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2019-08-20 19:20:17 -07:00 |
Eddie Hung
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d46dc9c5b4
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ecp5 to use -max_iter 1
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2019-08-20 19:18:36 -07:00 |
Eddie Hung
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55acf3120f
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ecp5 to use abc_map.v and _unmap.v
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2019-08-20 18:59:03 -07:00 |
Eddie Hung
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4cd1d21bfe
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Add (* abc_arrival=<int> *) doc
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2019-08-20 18:27:16 -07:00 |
Eddie Hung
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343039496b
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Add reference to FD* timing
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2019-08-20 18:22:58 -07:00 |
Eddie Hung
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091bf4a18b
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Remove sequential extension
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2019-08-20 18:16:37 -07:00 |
Eddie Hung
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bbab608691
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Remove SRL* delays from cells_sim.v
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2019-08-20 18:14:40 -07:00 |
Eddie Hung
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fad15d276d
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retime_mode -> dff_mode
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2019-08-20 18:08:58 -07:00 |
Eddie Hung
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aa2d3af631
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LUTMUX -> LUTMUX6
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2019-08-20 18:08:07 -07:00 |
Eddie Hung
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30a379b5b6
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Cleanup techmap in map_luts
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2019-08-20 17:59:31 -07:00 |
Eddie Hung
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3b52d6e29c
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Move `techmap abc_map.v` into map_luts
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2019-08-20 17:55:12 -07:00 |
Eddie Hung
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54284aaa98
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Remove delays from abc_map.v
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2019-08-20 17:52:27 -07:00 |
Eddie Hung
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96f00e9147
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Typo
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2019-08-20 17:51:50 -07:00 |
Eddie Hung
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8f666ebac1
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-20 17:36:14 -07:00 |
Eddie Hung
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1b5d2de1d4
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Do not sigmap!
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2019-08-20 15:23:26 -07:00 |
Eddie Hung
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0ca397f087
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Deprecate `abc_scc_break` attribute
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2019-08-20 15:10:01 -07:00 |
Eddie Hung
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e273ed5275
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Wrap SRL{16,32} too
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2019-08-20 15:09:38 -07:00 |
Eddie Hung
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808f07630f
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Wrap LUTRAMs in order to capture comb/seq behaviour
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2019-08-20 14:49:11 -07:00 |
Eddie Hung
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c00d72cdb3
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Minor refactor
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2019-08-20 14:47:58 -07:00 |
Eddie Hung
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0079e9b4a6
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Add LUTRAM delays
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2019-08-20 13:53:38 -07:00 |
Eddie Hung
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505d062daf
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Fix use of {CLK,EN}_POLARITY, also add a FIXME
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2019-08-20 13:33:31 -07:00 |
Eddie Hung
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8d0cffaf20
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Remove mapping rules
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2019-08-20 13:11:39 -07:00 |
Eddie Hung
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33960dd3d8
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Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
[WIP] synth xilinx renaming, as per #1184
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2019-08-20 12:55:26 -07:00 |
Eddie Hung
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5eda5fc7eb
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Remove -icells
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2019-08-20 12:41:11 -07:00 |
Eddie Hung
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be9e4f1b67
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Use abc_{map,unmap,model}.v
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2019-08-20 12:39:11 -07:00 |
Eddie Hung
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c4d4c6db3f
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-20 12:00:12 -07:00 |
Eddie Hung
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14c03861b6
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Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
Refactor abc9 to use port attributes, not module attributes
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2019-08-20 11:59:31 -07:00 |
Eddie Hung
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d9fe4cccbf
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
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2019-08-20 11:57:52 -07:00 |
SergeyDegtyar
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71dd412ac5
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Fix tests; Remove simulation;
- Add -map and -assert options for equiv_opt;
!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
- dffs;
- div_mod;
- latches;
- mul_pow;
- Add design -load;
- Remove simulations;
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2019-08-20 15:52:25 +03:00 |
Clifford Wolf
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ba71e4f8f2
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Merge pull request #1298 from YosysHQ/clifford/pmgen
Improvements in pmgen
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2019-08-20 11:39:42 +02:00 |
Clifford Wolf
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d0117d7d12
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Merge branch 'master' into clifford/pmgen
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2019-08-20 11:39:23 +02:00 |
Clifford Wolf
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6ffb910d12
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Add test case for real parameters
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-20 11:38:21 +02:00 |
Clifford Wolf
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c25c1e742b
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Merge pull request #1308 from jakobwenzel/real_params
Handle real values when deriving ast modules
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2019-08-20 11:37:26 +02:00 |
SergeyDegtyar
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153ec0541c
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Add new tests for ice40 architecture
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2019-08-20 07:50:05 +03:00 |
whitequark
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749ff864aa
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Merge pull request #1309 from whitequark/proc_clean-fix-1268
proc_clean: fix order of switch insertion
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2019-08-20 00:45:41 +00:00 |
Eddie Hung
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1f03154a0c
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-19 15:19:32 -07:00 |
Eddie Hung
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526e081342
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Add arrival times for SRL outputs
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2019-08-19 15:15:43 -07:00 |
Eddie Hung
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45d4b33f0c
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Output i/o/h extensions even if no boxes or flops
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2019-08-19 13:17:31 -07:00 |
Eddie Hung
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b71212ddea
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Add BRAM arrival times
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2019-08-19 12:46:35 -07:00 |
Eddie Hung
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e29df7d5fa
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Remove debug
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2019-08-19 12:44:43 -07:00 |
Eddie Hung
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2f86366087
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Add reference to source of Tclktoq timing
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2019-08-19 12:39:22 -07:00 |
Eddie Hung
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91687d3fea
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Add (* abc_arrival *) attribute
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2019-08-19 12:33:24 -07:00 |
Eddie Hung
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d02ef8c73f
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Add 'abc_arrival' attribute for flop outputs
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2019-08-19 11:32:18 -07:00 |
Eddie Hung
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f25837f8e8
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Update box timings
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2019-08-19 11:31:40 -07:00 |
Eddie Hung
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ba2261e21a
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Move from cell attr to module attr
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2019-08-19 11:18:33 -07:00 |
Eddie Hung
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3f4886e7a3
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Fix typo
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2019-08-19 10:42:00 -07:00 |
Eddie Hung
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7e010834eb
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Fix typo
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2019-08-19 10:41:18 -07:00 |
Eddie Hung
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f42ba811b6
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ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc
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2019-08-19 10:11:47 -07:00 |