Eddie Hung
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
N. Engelhardt
282d331e7e
Merge pull request #1716 from zeldin/ecp5_fix
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ecp5: remove unused parameter from \$__ECP5_PDPW16KD
2020-03-09 11:04:08 +01:00
N. Engelhardt
8a39a580e1
remove unused parameters
2020-03-06 16:45:36 +01:00
Eddie Hung
a85c55113f
synth_ecp5: use +/abc9_model.v
2020-02-27 10:17:29 -08:00
Eddie Hung
d2284715fa
ecp5: remove small LUT entries
2020-02-27 10:17:29 -08:00
Eddie Hung
46a89d7264
ecp5: deprecate abc9_{arrival,required} and *.{lut,box}
2020-02-27 10:17:29 -08:00
Marcus Comstedt
48a9b4f616
ecp5: Add missing parameter to \$__ECP5_PDPW16KD
2020-02-22 15:51:25 +01:00
whitequark
081d9318bc
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
...
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 16:52:51 +00:00
Eddie Hung
0b0148399c
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
Eddie Hung
ce6a690d27
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
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Now done in read_aiger
2020-01-27 13:30:27 -08:00
Eddie Hung
94ab3791ce
Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs
2020-01-07 15:44:18 -08:00
Eddie Hung
53aa51dc92
Re-enable &mfs for synth_{ecp5,xilinx}
2020-01-06 16:21:04 -08:00
Eddie Hung
19541640ee
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-06 09:31:28 -08:00
whitequark
f8d5920a7e
Merge pull request #1604 from whitequark/unify-ram-naming
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Harmonize BRAM/LUTRAM descriptions across all of Yosys
2020-01-02 21:06:17 +00:00
Eddie Hung
b454735bea
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 12:44:06 -08:00
whitequark
550310e264
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
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This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 12:30:00 +00:00
Eddie Hung
f7793a2956
Missing character
2019-12-31 18:42:11 -08:00
Eddie Hung
b2046a2114
Cleanup ecp5 boxes
2019-12-31 18:29:29 -08:00
Eddie Hung
79448f9be0
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
Eddie Hung
aa6d06c1b5
Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
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This reverts commit 6008bb7002
.
2019-12-30 13:28:29 -08:00
Eddie Hung
71906fab51
Nitpick cleanup for ecp5
2019-12-27 16:57:08 -08:00
Eddie Hung
10e82e103f
Revert "Optimise write_xaiger"
2019-12-20 12:05:45 -08:00
Eddie Hung
df626ee7ab
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
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Optimise write_xaiger
2019-12-19 12:24:03 -05:00
David Shah
520f1646cf
Merge pull request #1563 from YosysHQ/dave/async-prld
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ecp5: Add support for mapping PRLD FFs
2019-12-18 19:42:17 +00:00
Eddie Hung
f022645cd2
Fix bitwidth mismatch; suppresses iverilog warning
2019-12-11 13:02:07 -08:00
David Shah
184c0e796a
ecp5: Add support for mapping PRLD FFs
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-07 13:04:36 +00:00
Eddie Hung
98c9ea605b
techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
2019-12-06 17:05:02 -08:00
David Shah
51e4e29bb1
ecp5: Use new autoname pass for better cell/net names
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-15 21:03:11 +00:00
David Shah
fa989e59e5
ecp5: Pass -nomfs to abc9
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Fixes #1459
Signed-off-by: David Shah <dave@ds0.me>
2019-10-20 10:30:41 +01:00
Sean Cross
82f60ba938
Makefile: don't assume python is called `python3`
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On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-19 14:04:52 +08:00
David Shah
e1d4e683b4
ecp5: Add ECLKBRIDGECS blackbox
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-11 14:50:33 +01:00
David Shah
7b1a6706d8
ecp5: Add attrmvcp to copy syn_useioff to driving FF
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-10 15:58:31 +01:00
David Shah
3b44e80d4b
ecp5: Set syn_useioff on IO FFs to enable packing
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-10 15:55:16 +01:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
9fef1df3c1
Panic over. Model was elsewhere. Re-arrange for consistency
2019-10-04 10:48:44 -07:00
David Shah
b424d374db
ecp5: Fix shuffle_enable port
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-01 14:14:46 +01:00
David Shah
7a1538cd36
ecp5: Add support for mapping 36-bit wide PDP BRAMs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-01 13:46:36 +01:00
Eddie Hung
84825f9378
Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once
2019-09-26 10:45:14 -07:00
Eddie Hung
e742478e1d
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-05 13:01:27 -07:00
Eddie Hung
3732d421c5
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-04 12:37:42 -07:00
Eddie Hung
696f854801
Rename box
2019-09-02 12:15:11 -07:00
Eddie Hung
2fa3857963
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-02 12:13:44 -07:00
Miodrag Milanovic
a3c16a0565
Fix TRELLIS_FF simulation model
2019-08-31 11:12:06 +02:00
David Shah
90b44113d8
ecp5_gsr: Fix typo
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-31 09:58:46 +01:00
Eddie Hung
723815b384
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-30 13:26:19 -07:00
Eddie Hung
f0fef90e9d
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 10:30:46 -07:00
David Shah
6919c0f9b0
Merge branch 'master' into xc7dsp
2019-08-30 13:57:15 +01:00
David Shah
91b46ed816
ecp5: Add simulation equivalence check for Diamond FF implementations
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-30 13:27:36 +01:00
whitequark
d9c621f9d1
ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.
2019-08-30 10:05:09 +00:00
whitequark
1e6b60d563
ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives.
2019-08-30 09:56:19 +00:00
whitequark
6fa8ce93e6
ecp5: add missing FD primitives.
2019-08-30 09:54:48 +00:00
whitequark
7e2825a2a4
ecp5: fix CEMUX on IFS/OFS primitives.
2019-08-30 09:42:33 +00:00
Eddie Hung
8d820a9884
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-28 15:19:10 -07:00
David Shah
fc001b4731
ecp5: Add GSR support
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-27 13:07:06 +01:00
Eddie Hung
455da57272
Fix spacing
2019-08-23 13:21:21 -07:00
Eddie Hung
85d39653ac
Remove unused model
2019-08-23 13:20:29 -07:00
Eddie Hung
d672b1ddec
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-23 11:26:55 -07:00
Eddie Hung
a270af00cc
Put abc_* attributes above port
2019-08-23 11:21:44 -07:00
Eddie Hung
6b1b03d9f7
ecp5: remove DPR16X4 from abc_unmap.v
2019-08-20 19:20:17 -07:00
Eddie Hung
d46dc9c5b4
ecp5 to use -max_iter 1
2019-08-20 19:18:36 -07:00
Eddie Hung
55acf3120f
ecp5 to use abc_map.v and _unmap.v
2019-08-20 18:59:03 -07:00
Eddie Hung
d81a090d89
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
2019-08-19 09:56:17 -07:00
Eddie Hung
1c57b1e7ea
Update abc_* attr in ecp5 and ice40
2019-08-16 15:56:57 -07:00
David Shah
0492b8b541
ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 15:18:59 +01:00
David Shah
cb84ed2326
ecp5: Bring up to date with mul2dsp changes
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 15:14:09 +01:00
Eddie Hung
e3d898dccb
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-07 13:44:08 -07:00
David Shah
a36fd8582e
ecp5: Make cells_sim.v consistent with nextpnr
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-07 14:19:31 +01:00
Eddie Hung
42e40dbd0a
Merge remote-tracking branch 'origin/master' into ice40dsp
2019-07-18 15:45:25 -07:00
whitequark
698ab9beee
synth_ecp5: rename dram to lutram everywhere.
2019-07-16 20:45:12 +00:00
whitequark
ba099bfe9b
synth_{ice40,ecp5}: more sensible pass label naming.
2019-07-16 20:41:51 +00:00
Eddie Hung
42f8e68e76
OUT port to Y in generic DSP
2019-07-15 14:45:47 -07:00
Eddie Hung
cea7441d8a
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-07-10 15:58:01 -07:00
Eddie Hung
6bbd286e03
Error out if -abc9 and -retime specified
2019-07-10 12:47:48 -07:00
David Shah
27b27b8781
synth_ecp5: Fix typo in copyright header
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-09 22:26:10 +01:00
David Shah
c865559f95
xc7: Map combinational DSP48E1s
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-08 19:15:25 +01:00
David Shah
269ff450f5
Add mul2dsp multiplier splitting rule and ECP5 mapping
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-08 18:42:09 +01:00
Eddie Hung
dd8d264bf5
install *_nowide.lut files
2019-06-29 19:37:04 -07:00
Eddie Hung
3f87575cb6
Disable boxing of ECP5 dist RAM due to regression
2019-06-28 09:46:36 -07:00
Eddie Hung
0318860b93
Add write address to abc_scc_break of ECP5 dist RAM
2019-06-28 09:45:48 -07:00
Eddie Hung
b9ddee0c87
Fix DO4 typo
2019-06-28 09:45:40 -07:00
Eddie Hung
9398921af1
Refactor for one "abc_carry" attribute on module
2019-06-27 16:07:14 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
4de25a1949
Add WE to ECP5 dist RAM's abc_scc_break too
2019-06-26 20:02:19 -07:00
Eddie Hung
a7a88109f5
Update comment on boxes
2019-06-26 20:00:15 -07:00
Eddie Hung
988e6163ab
Add _nowide variants of LUT libraries in -nowidelut flows
2019-06-26 10:23:29 -07:00
Eddie Hung
799b18263f
Merge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 10:04:01 -07:00
Eddie Hung
4ce329aefd
synth_ecp5 rename -nomux to -nowidelut, but preserve former
2019-06-26 09:33:48 -07:00
Eddie Hung
4fadb471a3
Re-enable dist RAM boxes for ECP5
2019-06-24 22:12:50 -07:00
Eddie Hung
a4a7e63d84
Revert "Re-enable dist RAM boxes for ECP5"
...
This reverts commit ca0225fcfa
.
2019-06-24 22:10:28 -07:00
Eddie Hung
ca0225fcfa
Re-enable dist RAM boxes for ECP5
2019-06-24 21:55:54 -07:00
Eddie Hung
6027549464
Add comments to ecp5 box
2019-06-22 14:33:47 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
David Shah
a0d3d2bb41
ecp5: Improve mapping of $alu when BI is used
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Signed-off-by: David Shah <dave@ds0.me>
2019-06-21 09:45:11 +01:00
Eddie Hung
b304744d15
Clean up
2019-06-18 09:50:37 -07:00
Eddie Hung
94314ae2d5
Comment out dist RAM boxing on ECP5 for now
2019-06-14 10:42:30 -07:00
Eddie Hung
ee428f73ab
Remove WIP ABC9 flop support
2019-06-14 10:37:52 -07:00
David Shah
9566573054
ecp5: Add abc9 option
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Signed-off-by: David Shah <dave@ds0.me>
2019-06-14 17:15:02 +01:00
whitequark
f3a26730b6
ECP5: implement all Diamond I/O buffer primitives.
2019-06-06 10:18:33 +00:00
Clifford Wolf
9d117eba9d
Add handling of init attributes in "opt_expr -undriven"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 14:46:12 +02:00