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6434 Commits

Author SHA1 Message Date
Eddie Hung bddd641290 Fix SB_MAC sim model -- do not sign extend internal products? 2019-07-18 21:03:54 -07:00
Eddie Hung 601fac97e4 Add params 2019-07-18 21:02:49 -07:00
Eddie Hung a777be3091 Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 20:37:39 -07:00
Eddie Hung 0157043b97 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-07-18 20:36:48 -07:00
Eddie Hung 15c2a79ab9 Do not define `DSP_SIGNEDONLY macro if no exists 2019-07-18 16:04:58 -07:00
Eddie Hung 42e40dbd0a Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 15:45:25 -07:00
Eddie Hung 09411dd996 ice40_dsp to accept $__MUL16X16 too 2019-07-18 15:38:28 -07:00
Eddie Hung 266c1ae122 synth_ice40 to decompose into 16x16 2019-07-18 15:38:09 -07:00
Eddie Hung 2339b7fc37 mul2dsp to create cells that can be interchanged with $mul 2019-07-18 15:37:35 -07:00
Eddie Hung 802470746c Check if RHS is empty first 2019-07-18 15:22:00 -07:00
Eddie Hung e22a752242 Make consistent 2019-07-18 15:21:23 -07:00
Eddie Hung 90ac147eb2 Do not autoremove ffP aor muxP 2019-07-18 15:02:41 -07:00
Eddie Hung 08fe63c61e Improve pattern matcher to match subsets of $dffe? cells 2019-07-18 14:08:18 -07:00
Eddie Hung 79d63479ea Improve A/B reg packing 2019-07-18 13:30:35 -07:00
Eddie Hung e075f0dda0 Do not autoremove A/B registers since they might have other consumers 2019-07-18 13:22:22 -07:00
Eddie Hung 0727b2c902 Fix xilinx_dsp index cast 2019-07-18 13:18:04 -07:00
Eddie Hung 8326af5418 Fix signed multiplier decomposition 2019-07-18 13:11:26 -07:00
Eddie Hung 5562cb08a4 Use single DSP_SIGNEDONLY macro 2019-07-18 13:09:55 -07:00
David Shah 9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups 
Assorted synth_intel cleanups from @bwidawsk
 2019-07-18 19:04:28 +01:00
Dan Ravensloft 0c999ac2c4 synth_intel: Use stringf 2019-07-18 19:02:23 +01:00
Eddie Hung 2024357f32 Working for unsigned 2019-07-18 10:53:18 -07:00
David Shah 8e0f7c18f1
Merge pull request #1207 from ZirconiumX/intel_new_pass_names 
synth_intel: rename for consistency with #1184
 2019-07-18 17:34:55 +01:00
Dan Ravensloft 50f5e29724 synth_intel: s/not family/no family/ 2019-07-18 17:28:21 +01:00
Eddie Hung d5cd2c80be Cleanup 2019-07-18 09:20:48 -07:00
Dan Ravensloft d5b3b3bc6f synth_intel: revert change to run_max10 2019-07-18 17:09:15 +01:00
Ben Widawsky 999811572a intel_synth: Fix help message 
cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.

Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:25 +01:00
Ben Widawsky f950a7a75d intel_synth: Small code cleanup to remove if ladder 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:12 +01:00
Ben Widawsky 809b94a67b intel_synth: Make family explicit and match 
The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:03 +01:00
Ben Widawsky 060e77c09b intel_synth: Minor code cleanups 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:05:54 +01:00
Dan Ravensloft c78ab8ebc5 synth_intel: rename for consistency with #1184 
Also fix a typo in the help message.
 2019-07-18 16:46:21 +01:00
Eddie Hung c76607b9bc Wrong wildcard symbol 2019-07-18 08:14:58 -07:00
Eddie Hung 20b7120d66 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-07-18 08:11:33 -07:00
Clifford Wolf e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels 
synth_{ice40,ecp5}: more sensible pass label naming
 2019-07-18 15:34:28 +02:00
Clifford Wolf 927f0caa9d
Merge pull request #1203 from whitequark/write_verilog-zero-width-values 
write_verilog: dump zero width constants correctly
 2019-07-18 15:31:27 +02:00
David Shah 16b0ccf04c mul2dsp: Lower partial products always have unsigned inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-18 11:33:37 +01:00
Eddie Hung e3f8e59f18 Make all operands signed 2019-07-17 14:25:40 -07:00
Eddie Hung 58e63feae1 Update comment 2019-07-17 13:26:17 -07:00
Eddie Hung 91629ee4b3 Pattern matcher to check pool of bits, not exactly 2019-07-17 12:45:25 -07:00
Eddie Hung 8dca8d486e Fix mul2dsp signedness 2019-07-17 12:44:52 -07:00
Eddie Hung 1b62b82e05 A_SIGNED == B_SIGNED so flip both 2019-07-17 11:34:18 -07:00
Eddie Hung d63f105708 SigSpec::remove_const() to return SigSpec& 2019-07-17 10:44:11 -07:00
Clifford Wolf 56c00e871f Remove old $pmux_safe code from write_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-17 11:49:04 +02:00
David Shah 82153059a1
Merge pull request #1204 from smunaut/fix_1187 
ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
 2019-07-17 07:55:26 +01:00
Eddie Hung 0b6d47f8bf Add DSP_{A,B}_SIGNEDONLY macro 2019-07-16 15:55:13 -07:00
Eddie Hung c501aa5ee8 Signedness 2019-07-16 15:54:27 -07:00
Eddie Hung 3f677fb0db Signed extension 2019-07-16 15:54:07 -07:00
Sylvain Munaut f28e38de99 ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map 
The new mapping introduced in 437fec0d88
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-07-16 23:57:15 +02:00
Eddie Hung 6390c535ba Revert drop down to 24x16 multipliers for all 2019-07-16 14:30:25 -07:00
Eddie Hung 569cd66764 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-07-16 14:18:36 -07:00
Eddie Hung 9616dbd125 Add support {A,B,P}REG packing 2019-07-16 14:06:32 -07:00