riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
10,782 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

53 Commits

Author SHA1 Message Date
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Zachary Snow fe74b0cd95 verilog: significant block scoping improvements 
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.

Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.

1. Unlabled generate blocks are now implicitly named according to the LRM in
   `label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
   synthetic unnamed generate block to avoid creating extra hierarchy levels
   where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
   of the topmost scope, which is necessary because such wires and cells often
   appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
   invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
   scope, completely deferring the inspection and elaboration of nested scopes;
   names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
   to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
   in largely the same manner as other blocks
     before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
      after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
   than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
   prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
   or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode

Addresses the following issues: 656, 2423, 2493
 2021-01-31 09:42:09 -05:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Eddie Hung 90236025b7 Missing (* mul2dsp *) for sliceB 2019-09-27 14:21:47 -07:00
Eddie Hung 27e5bf5aad Stop trying to be too smart by prematurely optimising 2019-09-26 09:57:11 -07:00
Eddie Hung 35aaa8d73a mul2dsp.v slice names 2019-09-25 22:58:55 -07:00
Eddie Hung 34aa3532fb Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit 2019-09-25 17:26:47 -07:00
Eddie Hung a4238637ac Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" 
This reverts commit 234738b103.
 2019-09-25 17:25:44 -07:00
Eddie Hung f4387e817c Revert "No need for $__mul anymore?" 
This reverts commit 1d875ac76a.
 2019-09-25 17:24:11 -07:00
Eddie Hung 234738b103 Remove _TECHMAP_CELLTYPE_ check since all $mul 2019-09-25 16:51:31 -07:00
Eddie Hung 1d875ac76a No need for $__mul anymore? 2019-09-25 14:06:21 -07:00
Eddie Hung ab46d9017b Fix signedness bug 2019-09-20 10:11:36 -07:00
Eddie Hung f2d030a70f Be sensitive to signedness 2019-09-10 15:14:55 -07:00
Eddie Hung 76eedee089 Really get rid of 'opt_expr -fine' by being explicit 2019-09-10 14:26:12 -07:00
Eddie Hung e35dfc5ab5 Only swap ports if $mul and not $__mul 2019-08-13 16:52:15 -07:00
Eddie Hung 2a1b98d478 Add DSP_A_MAXWIDTH_PARTIAL, refactor 2019-08-13 10:21:24 -07:00
Eddie Hung 105aaeaf59 Trim Y_WIDTH 2019-08-01 14:33:16 -07:00
Eddie Hung 65de9aaaa9 Add DSP_SIGNEDONLY back 2019-08-01 14:29:00 -07:00
Eddie Hung 915f4e34bf DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH 2019-08-01 13:20:34 -07:00
Eddie Hung 332b86491d Revert "Do not do sign extension in techmap; let packer do it" 
This reverts commit 595a8f032f.
 2019-08-01 12:17:14 -07:00
Eddie Hung 7e86c8bcfb Fix B_WIDTH > DSP_B_MAXWIDTH case 2019-08-01 10:01:43 -07:00
Eddie Hung d2c33863d0 Do not compute sign bit if result is zero 2019-07-31 16:04:19 -07:00
Eddie Hung 60c4887d15 For signed multipliers, compute sign bit separately... 2019-07-31 15:45:41 -07:00
Eddie Hung 2f71c2c219 Fix spacing 2019-07-26 15:30:51 -07:00
Eddie Hung c39ccc65e9 Add copyright header, comment on cascade 2019-07-24 10:49:09 -07:00
Eddie Hung 151c5c96c0 Typo for Y_WIDTH 2019-07-23 15:05:20 -07:00
Eddie Hung 3a7aeb028d Use minimum sized width wires 2019-07-22 13:01:26 -07:00
Eddie Hung 47fd042b9f Indirection via $__soft_mul 2019-07-19 20:20:33 -07:00
Eddie Hung 595a8f032f Do not do sign extension in techmap; let packer do it 2019-07-19 15:50:13 -07:00
Eddie Hung bba72f03dd Do not $mul -> $__mul if A and B are less than maxwidth 2019-07-19 11:54:26 -07:00
Eddie Hung 1d14cec7fd Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too 2019-07-19 11:39:24 -07:00
Eddie Hung 7bdb3996e2 Merge branch 'xc7dsp' into ice40dsp 2019-07-19 10:28:38 -07:00
Eddie Hung ca94c2d3c4 Fix typo in B 2019-07-19 10:27:44 -07:00
Eddie Hung 2168568f43 Use sign_headroom instead 2019-07-19 09:16:13 -07:00
Eddie Hung 15c2a79ab9 Do not define `DSP_SIGNEDONLY macro if no exists 2019-07-18 16:04:58 -07:00
Eddie Hung 2339b7fc37 mul2dsp to create cells that can be interchanged with $mul 2019-07-18 15:37:35 -07:00
Eddie Hung e22a752242 Make consistent 2019-07-18 15:21:23 -07:00
Eddie Hung 8326af5418 Fix signed multiplier decomposition 2019-07-18 13:11:26 -07:00
Eddie Hung 2024357f32 Working for unsigned 2019-07-18 10:53:18 -07:00
Eddie Hung d5cd2c80be Cleanup 2019-07-18 09:20:48 -07:00
David Shah 16b0ccf04c mul2dsp: Lower partial products always have unsigned inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-18 11:33:37 +01:00
Eddie Hung 8dca8d486e Fix mul2dsp signedness 2019-07-17 12:44:52 -07:00
Eddie Hung 1b62b82e05 A_SIGNED == B_SIGNED so flip both 2019-07-17 11:34:18 -07:00
Eddie Hung 0b6d47f8bf Add DSP_{A,B}_SIGNEDONLY macro 2019-07-16 15:55:13 -07:00
Eddie Hung 569cd66764 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-07-16 14:18:36 -07:00
David Shah 8da4c1ad82 mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 16:44:40 +01:00
David Shah 7a75f5f3ac mul2dsp: Fix indentation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 16:19:32 +01:00
Eddie Hung fd5b3593d8 Do not swap if equals 2019-07-15 16:52:37 -07:00
Eddie Hung 42f8e68e76 OUT port to Y in generic DSP 2019-07-15 14:45:47 -07:00
Eddie Hung 91fcf034bc Only swap if B_WIDTH > A_WIDTH 2019-07-15 11:24:11 -07:00