Clifford Wolf
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6166c76831
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Added "yosys -A"
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2014-07-31 01:05:27 +02:00 |
Clifford Wolf
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e5c245df9d
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Added "yosys -Q"
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2014-07-31 00:53:21 +02:00 |
Clifford Wolf
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2541489105
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Added techmap CONSTMAP feature
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2014-07-30 22:04:30 +02:00 |
Clifford Wolf
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7daad40ca4
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Fixed counting verilog line numbers for "// synopsys translate_off" sections
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2014-07-30 20:18:48 +02:00 |
Clifford Wolf
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6400ae3648
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Added write_file command
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2014-07-30 19:59:29 +02:00 |
Clifford Wolf
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7d98645fe8
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Added "make -j{N}" support to "make test"
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2014-07-30 19:23:26 +02:00 |
Clifford Wolf
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ceecf5b153
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Improvements in test_cell
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2014-07-30 18:49:12 +02:00 |
Clifford Wolf
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6c05badc43
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New techmap default rules for $shr $sshr $shl $sshl
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2014-07-30 18:49:12 +02:00 |
Clifford Wolf
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3f0a5746ef
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Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models
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2014-07-30 18:37:17 +02:00 |
Clifford Wolf
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9b566a7efa
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Added native support for shift operations to ezSAT
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2014-07-30 18:37:17 +02:00 |
Clifford Wolf
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45fd26b76e
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Added "log_dump_val_worker(char *v)"
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2014-07-30 15:58:21 +02:00 |
Clifford Wolf
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e2a029b5d5
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Added CodingStyle document
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2014-07-30 14:10:49 +02:00 |
Clifford Wolf
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a7c6b37abf
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Added "kernel/yosys.h" and "kernel/yosys.cc"
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2014-07-30 14:10:15 +02:00 |
Clifford Wolf
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273383692a
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Added "test_cell" command
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2014-07-29 22:07:41 +02:00 |
Clifford Wolf
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e6df25bf74
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Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
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2014-07-29 21:12:50 +02:00 |
Clifford Wolf
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e605af8a49
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Fixed Verilog pre-processor for files with no trailing newline
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2014-07-29 20:14:25 +02:00 |
Clifford Wolf
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2145e57ef0
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Bugfix in simlib.v for iverilog
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2014-07-29 19:23:31 +02:00 |
Clifford Wolf
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77e2d39cd0
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Allow "hierarchy -generate" for $__ cells
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2014-07-29 16:35:13 +02:00 |
Clifford Wolf
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03c96f9ce7
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Added "techmap -map %{design-name}"
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2014-07-29 16:35:13 +02:00 |
Clifford Wolf
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397b00252d
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Added $shift and $shiftx cell types (needed for correct part select behavior)
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2014-07-29 16:35:13 +02:00 |
Clifford Wolf
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48822e79a3
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Removed left over debug code
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2014-07-28 19:38:30 +02:00 |
Clifford Wolf
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ec58965967
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Fixed part selects of parameters
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2014-07-28 19:24:28 +02:00 |
Clifford Wolf
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a03297a7df
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Set results of out-of-bounds static bit/part select to undef
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2014-07-28 16:09:50 +02:00 |
Clifford Wolf
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55521c085a
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Fixed RTLIL code generator for part select of parameter
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2014-07-28 15:31:19 +02:00 |
Clifford Wolf
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0598bc8708
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Fixed width detection for part selects
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2014-07-28 15:19:34 +02:00 |
Clifford Wolf
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27a872d1e7
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Added support for "upto" wires to Verilog front- and back-end
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2014-07-28 14:25:03 +02:00 |
Clifford Wolf
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3c45277ee0
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Added wire->upto flag for signals such as "wire [0:7] x;"
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2014-07-28 12:12:13 +02:00 |
Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
Clifford Wolf
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d86a25f145
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Added std::initializer_list<> constructor to SigSpec
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2014-07-28 10:52:58 +02:00 |
Clifford Wolf
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f99495a895
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Added cover() to all SigSpec constructors
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2014-07-28 10:52:30 +02:00 |
Clifford Wolf
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ee65dea738
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Fixed signdness detection of expressions with bit- and part-selects
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2014-07-28 10:10:08 +02:00 |
Clifford Wolf
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c469be883b
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Improvements in tests/vloghtb
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2014-07-28 09:15:40 +02:00 |
Clifford Wolf
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8b0f50792c
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Added techmap -extern
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2014-07-27 21:31:18 +02:00 |
Clifford Wolf
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c4bdba78cb
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Added proper Design->addModule interface
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2014-07-27 21:12:09 +02:00 |
Clifford Wolf
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5da343b7de
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Added topological sorting to techmap
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2014-07-27 16:43:39 +02:00 |
Clifford Wolf
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0c86d6106c
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Added SigPool::check(bit)
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2014-07-27 15:38:02 +02:00 |
Clifford Wolf
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ddd31a0b66
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Small improvements in PerformanceTimer API
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2014-07-27 15:14:02 +02:00 |
Clifford Wolf
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77a1462f2d
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Fixed bug in opt_clean
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2014-07-27 15:13:29 +02:00 |
Clifford Wolf
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d07a871d35
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Improved performance of opt_const on large modules
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2014-07-27 14:50:25 +02:00 |
Clifford Wolf
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4be645860b
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Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
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2014-07-27 14:47:48 +02:00 |
Clifford Wolf
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cbc3a46a97
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Added RTLIL::SigSpecConstIterator
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2014-07-27 14:47:23 +02:00 |
Clifford Wolf
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dbb3556e3f
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Fixed a bug in opt_clean and some RTLIL API usage cleanups
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2014-07-27 13:19:05 +02:00 |
Clifford Wolf
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d878fcbdc7
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Added log_cmd_error_expection
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2014-07-27 12:05:50 +02:00 |
Clifford Wolf
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7661ded8dd
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Fixed verific bindings for new RTLIL api
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2014-07-27 12:00:28 +02:00 |
Clifford Wolf
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6b34215efd
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Fixed ilang parser for new RTLIL API
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2014-07-27 11:56:35 +02:00 |
Clifford Wolf
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49f72421d5
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Using new obj iterator API in a few places
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2014-07-27 11:32:42 +02:00 |
Clifford Wolf
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675cb93da9
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Added RTLIL::Module::wire(id) and cell(id) lookup functions
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2014-07-27 11:18:31 +02:00 |
Clifford Wolf
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0bd8fafbd2
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Added RTLIL::Design::modules()
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2014-07-27 11:18:30 +02:00 |
Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
Clifford Wolf
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d088854b47
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Added conversion from ObjRange to std::vector and std::set
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2014-07-27 11:18:30 +02:00 |