Eddie Hung
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428d7c8e11
|
Remove unused function
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2019-05-27 13:49:42 -07:00 |
Eddie Hung
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e115e736fa
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parse_xaiger to not parse symbol table
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2019-05-27 12:34:17 -07:00 |
Eddie Hung
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234156c01a
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Instantiate cell type (from sym file) otherwise 'clean' warnings
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2019-05-27 12:16:10 -07:00 |
Eddie Hung
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03b289a851
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Add 'cinput' and 'coutput' to symbols file for boxes
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2019-05-27 11:38:52 -07:00 |
Eddie Hung
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68359bcd6f
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Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
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2019-05-23 13:37:53 -07:00 |
Eddie Hung
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7057753427
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Rename label
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2019-05-21 18:20:31 -07:00 |
Eddie Hung
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b5a29460b9
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Try again
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2019-05-21 17:20:19 -07:00 |
Eddie Hung
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1bff09f2ff
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Fix warning
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2019-05-21 16:26:20 -07:00 |
Eddie Hung
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9d122d3c51
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Refactor into AigerReader::post_process()
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2019-04-23 15:06:19 -07:00 |
Eddie Hung
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eaf3c24772
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Temporarily remove 'r' extension
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2019-04-22 11:54:19 -07:00 |
Eddie Hung
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4883391b63
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Merge remote-tracking branch 'origin/master' into xaig
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2019-04-22 11:19:52 -07:00 |
Clifford Wolf
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e158ea2097
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Add log_debug() framework
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-22 17:25:52 +02:00 |
Eddie Hung
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21701cc1df
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read_aiger to parse 'r' extension
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2019-04-18 17:39:36 -07:00 |
Eddie Hung
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e1b550d203
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Ignore a/i/o/h XAIGER extensions
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2019-04-17 10:55:23 -07:00 |
Eddie Hung
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fecafb2207
|
Forgot backslashes
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2019-04-12 18:22:44 -07:00 |
Eddie Hung
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9bfcd80063
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Handle __dummy_o__ and __const[01]__ in read_aiger not abc
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2019-04-12 18:21:16 -07:00 |
Eddie Hung
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c776db3320
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
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2019-04-12 17:09:24 -07:00 |
Eddie Hung
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acf3f5694b
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Fix inout handling for -map option
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2019-04-12 17:02:24 -07:00 |
Eddie Hung
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ada130b459
|
Also cope with duplicated CIs
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2019-04-12 16:17:12 -07:00 |
Eddie Hung
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1c6f0cffd9
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Cope with an output having same name as an input (i.e. CO)
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2019-04-12 12:27:07 -07:00 |
Eddie Hung
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1a49cf29d8
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parse_aiger() to rename all $lut cells after "clean"
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2019-04-10 14:02:23 -07:00 |
Eddie Hung
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36efec01b8
|
Fix spacing
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2019-04-08 16:37:22 -07:00 |
Eddie Hung
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da076344cc
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parse_xaiger() to really pass single and multi-bit inout tests
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2019-02-26 12:04:45 -08:00 |
Eddie Hung
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8f02c846f6
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parse_xaiger() to cope with multi bit inouts
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2019-02-26 11:37:34 -08:00 |
Eddie Hung
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316232a7dd
|
parse_xaiger() to untransform $inout.out output ports
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2019-02-25 18:40:23 -08:00 |
Eddie Hung
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721f6a14fb
|
read_aiger to accept empty string for clk_name, passable only if no latches
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2019-02-25 15:34:02 -08:00 |
Eddie Hung
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07036b8bf7
|
read_aiger to work with symbol table
|
2019-02-21 17:01:07 -08:00 |
Eddie Hung
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085ed9f487
|
Add attribution
|
2019-02-21 14:40:13 -08:00 |
Eddie Hung
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3307295488
|
Merge branch 'read_aiger' into xaig
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2019-02-21 14:27:32 -08:00 |
Eddie Hung
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9e299a0908
|
read_aiger to not do -purge for clean
|
2019-02-20 17:33:04 -08:00 |
Eddie Hung
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32853b1f8d
|
lut/not/and suffix to be ${lut,not,and}
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2019-02-20 16:30:30 -08:00 |
Eddie Hung
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abc1c2672e
|
read_aiger to also rename 0 index lut when wideports
|
2019-02-20 16:17:22 -08:00 |
Eddie Hung
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f9702a8abe
|
read_aiger: new naming fixes
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2019-02-20 12:39:51 -08:00 |
Eddie Hung
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83b66861e9
|
read_aiger to name wires with internal name, less likely to clash
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2019-02-20 11:22:56 -08:00 |
Eddie Hung
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7b026c4bc3
|
Same for ascii AIGERs too
|
2019-02-19 15:15:50 -08:00 |
Eddie Hung
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d304882cba
|
read_aiger to cope with non-unique POs
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2019-02-19 15:14:08 -08:00 |
Eddie Hung
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e79df5e70e
|
read_aiger to create sane $lut names, and rename when renaming driving wire
|
2019-02-19 12:27:50 -08:00 |
Eddie Hung
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0b1fc46ae3
|
Add comment
|
2019-02-19 10:24:55 -08:00 |
Eddie Hung
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54f719f446
|
Get rid of boost dep, fix the FIXMEs for Win32?
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2019-02-19 10:19:53 -08:00 |
Eddie Hung
|
843e7fc8a7
|
Fix for using POSIX basename
|
2019-02-19 09:02:37 -08:00 |
Eddie Hung
|
8e1dbfac3a
|
Missing OSX headers?
|
2019-02-17 20:59:53 -08:00 |
Eddie Hung
|
9268a271fb
|
read_aiger to ignore line after ands for ascii, not binary
|
2019-02-17 12:07:14 -08:00 |
Eddie Hung
|
82459c16c4
|
In read_xaiger, do not construct ConstEval for every LUT
|
2019-02-16 22:22:29 -08:00 |
Eddie Hung
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f60cd4ff9b
|
read_aiger to ignore output = input of same wire; also create new output for different wire
|
2019-02-16 21:53:03 -08:00 |
Eddie Hung
|
1a25ec4baa
|
read_aiger to disable log_debug
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2019-02-16 13:45:51 -08:00 |
Eddie Hung
|
8f36013fac
|
read_xaiger() to use f.read() not readsome()
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2019-02-16 08:58:25 -08:00 |
Eddie Hung
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7523c87780
|
read_aiger() to cope with constant outputs, mixed wideports, do cleaning
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2019-02-16 08:44:11 -08:00 |
Eddie Hung
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8d757224ee
|
read_aiger with more asserts, and call clean
|
2019-02-15 11:52:05 -08:00 |
Eddie Hung
|
c7ef3863f3
|
Leave FIXME for clean
|
2019-02-13 17:19:30 -08:00 |
Eddie Hung
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396da54b52
|
Use module->addLut()
|
2019-02-13 17:08:32 -08:00 |