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244 Commits

Author SHA1 Message Date
Miodrag Milanovic a07b06d5e7 Update Changelog 2022-08-03 13:52:01 +02:00
Miodrag Milanovic 6a1d98b816 Update manual and changelog 2022-08-03 10:30:58 +02:00
Miodrag Milanovic da0682b99a Next dev cycle 2022-07-04 14:08:53 +02:00
Miodrag Milanovic a45c131b37 Release version 0.19 2022-07-04 14:07:01 +02:00
Jannis Harder 5343911263 Mention smtlib2_module in README.md and CHANGELOG 2022-07-04 13:54:49 +02:00
Miodrag Milanovic 59b96bb1f8 Upadte documentation and changelog 2022-07-04 11:09:06 +02:00
Miodrag Milanovic 4b423dcfb4 Next dev cycle 2022-06-10 15:05:09 +02:00
Miodrag Milanovic 19ce3b45d6 Release version 0.18 2022-06-10 15:01:40 +02:00
Miodrag Milanovic 1940bf647f Updated CHANGELOG 2022-06-10 09:08:23 +02:00
Miodrag Milanovic 6e8e4b4550 verific: Added "-vlog-libext" option to specify search extension for libraries 2022-06-09 08:57:48 +02:00
Miodrag Milanovic a0172e68c5 More updates on CHANGELOG 2022-06-08 11:41:13 +02:00
Miodrag Milanovic 096f3d2aa4 Update changelog and manual 2022-06-08 11:28:06 +02:00
Zachary Snow a650d9079f verilog: fix width/sign detection for functions 2022-05-30 16:45:39 -04:00
Jannis Harder 4bfaaea0d5 verilog: fix size and signedness of array querying functions 
genrtlil.cc and simplify.cc had inconsistent and slightly broken
handling of signedness for array querying functions. These functions are
defined to return a signed result. Simplify always produced an unsigned
and genrtlil always a signed 32-bit result ignoring the context.

Includes tests for the the relvant edge cases for context dependent
conversions.
 2022-05-30 09:11:31 -04:00
Jannis Harder b75fa62e9b verilog: fix $past's signedness 2022-05-25 16:32:08 -04:00
Jannis Harder cffec1f95f verilog: fix signedness when removing unreachable cases 2022-05-24 23:03:31 -04:00
Miodrag Milanovic d562bfd165 Next dev cycle 2022-05-09 10:12:32 +02:00
Miodrag Milanovic 6f9602b4cf Release version 0.17 2022-05-09 10:11:04 +02:00
Miodrag Milanovic 72d2efeb32 Update CHANGELOG 2022-05-09 10:06:15 +02:00
Zachary Snow bf15dbd0f7 sv: fix always_comb auto nosync for nested and function blocks 2022-04-05 14:43:48 -06:00
Miodrag Milanovic 957fdb328a Next dev cycle 2022-04-05 11:50:49 +02:00
Miodrag Milanovic b63e0a0cae Release version 0.16 2022-04-05 11:49:37 +02:00
Miodrag Milanovic 0d3bf9e725 Update CHANGELOG and manual 2022-04-04 16:53:47 +02:00
Miodrag Milanovic 7be7f5e02e Next dev cycle 2022-03-04 11:37:18 +01:00
Miodrag Milanovic 07a43689d8 Release version 0.15 2022-03-04 11:36:03 +01:00
Miodrag Milanovic 3818e1160d Update CHANGELOG 2022-03-02 14:26:15 +01:00
Zachary Snow 15a4e900b2 verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00
Kamil Rakoczy 68c67c40ec
Fix access to whole sub-structs (#3086) 
* Add support for accessing whole struct
* Update tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2022-02-14 14:34:20 +01:00
Zachary Snow 15eb66b99d verilog: fix dynamic dynamic range asgn elab 2022-02-11 22:54:55 +01:00
Zachary Snow 90bb47d181 verilog: fix const func eval with upto variables 2022-02-11 21:01:51 +01:00
Miodrag Milanovic 818060880d Next dev cycle 2022-02-07 17:10:50 +01:00
Miodrag Milanovic a4522d6282 Release version 0.14 2022-02-07 17:08:39 +01:00
Miodrag Milanovic 9647f6326f Update CHANGELOG and manual 2022-02-07 17:07:48 +01:00
Miodrag Milanovic c428a894c0 Next dev cycle 2022-01-11 08:39:34 +01:00
Miodrag Milanovic 8b1eafc3ad Release version 0.13 2022-01-11 08:35:50 +01:00
Miodrag Milanovic 64972360a8 Update CHANGELOG 2022-01-11 08:21:12 +01:00
Zachary Snow aa35f24290 sv: auto add nosync to certain always_comb local vars 
If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
 2022-01-07 22:53:22 -07:00
Zachary Snow 828e85068f sv: fix size cast internal expression extension 2022-01-07 21:21:02 -07:00
Zachary Snow 8c509a5659 sv: fix size cast clipping expression width 2022-01-03 08:17:35 -07:00
Zachary Snow 7608985d2c fix width detection of array querying function in case and case item expressions 
I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
 2021-12-17 21:22:08 -07:00
Miodrag Milanovic c23cd00f30 Next dev cycle 2021-12-03 12:51:34 +01:00
Miodrag Milanovic 2156e20db5 Release version 0.12 2021-12-03 12:48:49 +01:00
Miodrag Milanovic 4792d925fc Update CHANGELOG and CODEOWNERS 2021-12-01 08:42:37 +01:00
Miodrag Milanovic a28ee81be0 Next dev cycle 2021-11-05 12:52:24 +01:00
Miodrag Milanovic 360fed8e4d Release version 0.11 2021-11-05 12:47:38 +01:00
Miodrag Milanovic 051b234df6 Add missing changelog item 2021-11-05 10:08:50 +01:00
Miodrag Milanovic c0edfa8788 Add missing items in CHANGELOG 2021-10-29 13:31:41 +02:00
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections 
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
 2021-10-25 18:25:50 -07:00
Marcelina Kościelnicka ec2b5548fe Add $aldff and $aldffe: flip-flops with async load. 2021-10-02 18:12:52 +02:00
Miodrag Milanovic 070cad5f4b Prepare for next release cycle 2021-09-27 16:24:43 +02:00
Zachary Snow d6fe6d4fb6 sv: support wand and wor of data types 
This enables the usage of declarations of wand or wor with a base type
of logic, integer, or a typename. Note that declarations of nets with
2-state base types is still permitted, in violation of the spec.
 2021-09-21 14:52:28 -04:00
Miodrag Milanović 1d52c07e9b
Updates for CHANGELOG (#2997) 
Added missing changes from git log and  group items
 2021-09-13 16:25:42 +02:00
Marcelina Kościelnicka fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka 19720b970d memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka dc07ae9677 techmap: Add _TECHMAP_CELLNAME_ special parameter. 
This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
 2020-07-21 15:00:54 +02:00
Marcelina Kościelnicka e3564b4502 Add dfflegalize pass. 2020-07-01 01:57:15 +02:00
Xiretza c34cb90a20
Update CHANGELOG 2020-05-28 22:59:04 +02:00
Eddie Hung c34d57de2e Update CHANGELOG and manual for departure from upstream 2020-04-27 12:08:45 -07:00
Eddie Hung 254d38ca67 select: add select -unset option 2020-04-16 10:51:58 -07:00
Eddie Hung a9ec0defb9 kernel: add design -delete option 2020-04-16 08:05:18 -07:00
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff. 
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
 2020-04-15 16:22:37 +02:00
Miodrag Milanovic d8735b2913 Add to changelog 2020-02-17 15:08:35 +01:00
Rodrigo A. Melo 665a967d87
Merge branch 'master' into master 2020-02-03 11:07:51 -03:00
Marcelina Kościelnicka 34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Rodrigo Alejandro Melo 313a425bd5 Merge branch 'master' of https://github.com/YosysHQ/yosys 
Solved a conflict into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:56:41 -03:00
David Shah 0488492ad2 Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:13:13 +00:00
Rodrigo Alejandro Melo 2774aae0f2 Removed a line jump into the CHANGELOG 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 22:56:01 -03:00
Rodrigo Alejandro Melo 7b3fe404ab $readmem[hb] file inclusion is now relative to the Verilog file 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-01-31 18:20:22 -03:00
Eddie Hung 345e98f871 Add 'abc9 -dff' to CHANGELOG 2020-01-02 12:42:28 -08:00
Eddie Hung ece423415c Add CHANGELOG entry, add abc9_{flop,keep} attr to README.md 2019-12-30 14:24:58 -08:00
Eddie Hung f52c6efd9d Add "scratchpad" to CHANGELOG 2019-12-18 12:09:11 -08:00
Marcin Kościelnicki a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
David Shah b60f32c6ec Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-22 12:46:19 +00:00
Clifford Wolf 45e4c040d7 Add "check -mapped" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-02 13:35:03 +02:00
Marcin Kościelnicki 4535f2c694 synth_xilinx: Support latches, remove used-up FF init values. 
Fixes #1387.
 2019-09-30 12:52:43 +02:00
Eddie Hung 3fb839e255 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-20 12:21:36 -07:00
Clifford Wolf c072e00a39 Update CHANGELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-20 10:28:20 +02:00
Eddie Hung b88f0f6450 Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
Eddie Hung 0020a18929 Add more entries 2019-09-19 12:00:39 -07:00
Marcin Kościelnicki c9f9518de4 Added extractinv pass 2019-09-19 04:02:48 +02:00
Eddie Hung a1123b095c Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-12 12:11:11 -07:00
Marcin Kościelnicki f72765090c Add -match-init option to dff2dffs. 2019-09-11 19:38:20 +02:00
Eddie Hung feb3fa65a3 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-11 00:01:31 -07:00
Eddie Hung 04153c5011 Update CHANGELOG 2019-09-10 16:14:26 -07:00
Marcin Kościelnicki a82e8df7d3 techmap: Add support for extracting init values of ports 2019-09-07 16:30:43 +02:00
Eddie Hung ba5d81c7f1 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
Eddie Hung 1ba09c4ab7 Merge branch 'master' into eddie/xilinx_srl 2019-08-26 13:56:31 -07:00
Eddie Hung a098205479 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-26 13:25:17 -07:00
Eddie Hung bd3773a17f Remove dupe in CHANGELOG, missing end quote 2019-08-26 10:44:23 -07:00
Clifford Wolf 8a4c6e6563 Merge tag 'yosys-0.9' 2019-08-26 11:14:22 +02:00
Eddie Hung cee30deef5 Mention shregmap -tech xilinx is superseded 2019-08-23 12:24:25 -07:00
Eddie Hung f4fd41d5d2 Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl 2019-08-23 11:35:06 -07:00
Eddie Hung 6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Clifford Wolf adb81ba386 Add pmgen slices and choices 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-23 16:15:50 +02:00
Eddie Hung 7a9031c48e Add CHANGELOG entry 2019-08-22 11:22:53 -07:00
Eddie Hung 33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx 
[WIP] synth xilinx renaming, as per #1184
 2019-08-20 12:55:26 -07:00
Eddie Hung d9fe4cccbf Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx 2019-08-20 11:57:52 -07:00
Clifford Wolf 1e3dd0a2da Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen 2019-08-19 13:04:06 +02:00