mirror of https://github.com/YosysHQ/yosys.git
Merge tag 'yosys-0.9'
This commit is contained in:
Clifford Wolf
commit
8a4c6e6563
116
CHANGELOG
116
CHANGELOG
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@ -13,6 +13,10 @@ Yosys 0.9 .. Yosys 0.9-dev
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- Added "synth_ice40 -abc9" (experimental)
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- Added "synth -abc9" (experimental)
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- Added "script -scriptwire
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- Added "synth_xilinx -nocarry"
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- Added "synth_xilinx -nowidelut"
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- Added "synth_ecp5 -nowidelut"
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- "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
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- "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
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- Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
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- Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
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@ -29,32 +33,124 @@ Yosys 0.9 .. Yosys 0.9-dev
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- Removed "ice40_unlut"
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- Improvements in pmgen: slices, choices, define, generate
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Yosys 0.8 .. Yosys 0.8-dev
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--------------------------
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Yosys 0.8 .. Yosys 0.9
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----------------------
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* Various
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- Added $changed support to read_verilog
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- Many bugfixes and small improvements
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- Added support for SystemVerilog interfaces and modports
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- Added "write_edif -attrprop"
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- Added "ice40_unlut" pass
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- Added "opt_lut" pass
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- Added "synth_ice40 -relut"
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- Added "synth_ice40 -noabc"
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- Added "gate2lut.v" techmap rule
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- Added "rename -src"
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- Added "equiv_opt" pass
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- Added "shregmap -tech xilinx"
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- Added "flowmap" LUT mapping pass
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- Added "rename -wire" to rename cells based on the wires they drive
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- Added "bugpoint" for creating minimised testcases
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- Added "write_edif -gndvccy"
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- "write_verilog" to escape Verilog keywords
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- Fixed sign handling of real constants
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- "write_verilog" to write initial statement for initial flop state
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- Added pmgen pattern matcher generator
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- Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
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- Added "setundef -params" to replace undefined cell parameters
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- Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
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- Fixed handling of defparam when default_nettype is none
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- Fixed "wreduce" flipflop handling
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- Fixed FIRRTL to Verilog process instance subfield assignment
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- Added "write_verilog -siminit"
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- Several fixes and improvements for mem2reg memories
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- Fixed handling of task output ports in clocked always blocks
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- Improved handling of and-with-1 and or-with-0 in "opt_expr"
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- Added "read_aiger" frontend
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- Added "mutate" pass
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- Added "hdlname" attribute
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- Added "rename -output"
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- Added "read_ilang -lib"
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- Improved "proc" full_case detection and handling
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- Added "whitebox" and "lib_whitebox" attributes
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- Added "read_verilog -nowb", "flatten -wb" and "wbflip"
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- Added Python bindings and support for Python plug-ins
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- Added "pmux2shiftx"
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- Added log_debug framework for reduced default verbosity
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- Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
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- Added "peepopt" peephole optimisation pass using pmgen
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- Added approximate support for SystemVerilog "var" keyword
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- Added parsing of "specify" blocks into $specrule and $specify[23]
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- Added support for attributes on parameters and localparams
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- Added support for parsing attributes on port connections
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- Added "wreduce -keepdc"
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- Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
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- Added Verilog wand/wor wire type support
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- Added support for elaboration system tasks
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- Added "muxcover -mux{4,8,16}=<cost>"
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- Added "muxcover -dmux=<cost>"
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- Added "muxcover -nopartial"
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- Added "muxpack" pass
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- Added "pmux2shiftx -norange"
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- Added support for "~" in filename parsing
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- Added "read_verilog -pwires" feature to turn parameters into wires
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- Fixed sign extension of unsized constants with 'bx and 'bz MSB
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- Fixed genvar to be a signed type
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- Added support for attributes on case rules
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- Added "upto" and "offset" to JSON frontend and backend
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- Several liberty file parser improvements
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- Fixed handling of more complex BRAM patterns
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- Add "write_aiger -I -O -B"
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* Formal Verification
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- Added $changed support to read_verilog
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- Added "read_verilog -noassert -noassume -assert-assumes"
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- Added btor ops for $mul, $div, $mod and $concat
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- Added yosys-smtbmc support for btor witnesses
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- Added "supercover" pass
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- Fixed $global_clock handling vs autowire
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- Added $dffsr support to "async2sync"
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- Added "fmcombine" pass
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- Added memory init support in "write_btor"
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- Added "cutpoint" pass
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- Changed "ne" to "neq" in btor2 output
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- Added support for SVA "final" keyword
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- Added "fmcombine -initeq -anyeq"
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- Added timescale and generated-by header to yosys-smtbmc vcd output
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- Improved BTOR2 handling of undriven wires
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* Verific support
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- Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
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- Improved support for asymmetric memories
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- Added "verific -chparam"
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- Fixed "verific -extnets" for more complex situations
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- Added "read -verific" and "read -noverific"
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- Added "hierarchy -chparam"
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* New back-ends
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- Added initial Anlogic support
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- Added initial SmartFusion2 and IGLOO2 support
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* ECP5 support
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- Added "synth_ecp5 -nowidelut"
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- Added BRAM inference support to "synth_ecp5"
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- Added support for transforming Diamond IO and flipflop primitives
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* iCE40 support
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- Added "ice40_unlut" pass
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- Added "synth_ice40 -relut"
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- Added "synth_ice40 -noabc"
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- Added "synth_ice40 -dffe_min_ce_use"
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- Added DSP inference support using pmgen
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- Added support for initialising BRAM primitives from a file
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- Added iCE40 Ultra RGB LED driver cells
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* Xilinx support
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- Use "write_edif -pvector bra" for Xilinx EDIF files
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- Fixes for VPR place and route support with "synth_xilinx"
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- Added more cell simulation models
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- Added "synth_xilinx -family"
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- Added "stat -tech xilinx" to estimate logic cell usage
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- Added "synth_xilinx -nocarry"
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- Added "synth_xilinx -nowidelut"
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- Added "synth_ecp5 -nowidelut"
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- "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
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- Fixed sign extension of unsized constants with 'bx and 'bz MSB
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- Added support for mapping RAM32X1D
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Yosys 0.7 .. Yosys 0.8
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----------------------
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2
Makefile
2
Makefile
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@ -115,7 +115,7 @@ LDFLAGS += -rdynamic
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LDLIBS += -lrt
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endif
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YOSYS_VER := 0.8+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 4d4665b.. 2> /dev/null | wc -l; })
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YOSYS_VER := 0.9+1
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GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
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OBJS = kernel/version_$(GIT_REV).o
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