From fdf0e82472d978ddbe0a287bdda8b5341b814d3e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 11:16:15 -0700
Subject: [PATCH 01/30] Add missing CHANGELOG entries

---
 CHANGELOG | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/CHANGELOG b/CHANGELOG
index 4d0c31e28..03ab2a7cc 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -23,6 +23,9 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "muxcover -nopartial"
     - Added "muxpack" pass
     - Added "pmux2shiftx -norange"
+    - Added "synth_xilinx -nocarry"
+    - Added "synth_xilinx -nowidelut"
+    - Added "synth_ecp5 -nowidelut"
     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 

From 43069e9eb91bf76164e80d6ea65443bd05567d64 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 2 Jul 2019 10:06:56 -0700
Subject: [PATCH 02/30] Checkout yosys-0.9-rc branch of yosys-tests

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 67bcb3d15..383ec9e55 100644
--- a/Makefile
+++ b/Makefile
@@ -702,7 +702,7 @@ vloghtb: $(TARGETS) $(EXTRA_TARGETS)
 
 ystests: $(TARGETS) $(EXTRA_TARGETS)
 	rm -rf tests/ystests
-	git clone https://github.com/YosysHQ/yosys-tests.git tests/ystests
+	git clone -b yosys-0.9-rc https://github.com/YosysHQ/yosys-tests.git tests/ystests
 	+$(MAKE) PATH="$$PWD:$$PATH" -C tests/ystests
 	@echo ""
 	@echo "  Finished \"make ystests\"."

From ef0823690c386c405fdd0ca2a3f45af8788a19aa Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 28 Jun 2019 10:30:31 +0200
Subject: [PATCH 03/30] Merge pull request #1146 from gsomlo/gls-test-abc-ext

tests: use optional ABCEXTERNAL when specified
---
 Makefile                   | 10 ++++++++--
 tests/aiger/run-test.sh    | 14 ++++++++++++--
 tests/memories/run-test.sh |  6 ++++--
 tests/tools/autotest.sh    |  7 +++++--
 4 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/Makefile b/Makefile
index 383ec9e55..bbae8c159 100644
--- a/Makefile
+++ b/Makefile
@@ -666,6 +666,12 @@ else
 SEEDOPT=""
 endif
 
+ifneq ($(ABCEXTERNAL),)
+ABCOPT="-A $(ABCEXTERNAL)"
+else
+ABCOPT=""
+endif
+
 test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/simple && bash run-test.sh $(SEEDOPT)
 	+cd tests/hana && bash run-test.sh $(SEEDOPT)
@@ -674,13 +680,13 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/share && bash run-test.sh $(SEEDOPT)
 	+cd tests/fsm && bash run-test.sh $(SEEDOPT)
 	+cd tests/techmap && bash run-test.sh
-	+cd tests/memories && bash run-test.sh $(SEEDOPT)
+	+cd tests/memories && bash run-test.sh $(ABCOPT) $(SEEDOPT)
 	+cd tests/bram && bash run-test.sh $(SEEDOPT)
 	+cd tests/various && bash run-test.sh
 	+cd tests/sat && bash run-test.sh
 	+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
 	+cd tests/opt && bash run-test.sh
-	+cd tests/aiger && bash run-test.sh
+	+cd tests/aiger && bash run-test.sh $(ABCOPT)
 	+cd tests/arch && bash run-test.sh
 	@echo ""
 	@echo "  Passed \"make test\"."
diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index 5246c1b48..deaf48a3d 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -2,6 +2,16 @@
 
 set -e
 
+OPTIND=1
+abcprog="../../yosys-abc"    # default to built-in version of abc
+while getopts "A:" opt
+do
+    case "$opt" in
+	A) abcprog="$OPTARG" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
 # NB: *.aag and *.aig must contain a symbol table naming the primary
 #     inputs and outputs, otherwise ABC and Yosys will name them
 #     arbitrarily (and inconsistently with each other).
@@ -11,7 +21,7 @@ for aag in *.aag; do
     # (which would have been created by the reference aig2aig utility,
     #  available from http://fmv.jku.at/aiger/)
     echo "Checking $aag."
-    ../../yosys-abc -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
+    $abcprog -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
     ../../yosys -qp "
 read_verilog ${aag%.*}_ref.v
 prep
@@ -28,7 +38,7 @@ done
 
 for aig in *.aig; do
     echo "Checking $aig."
-    ../../yosys-abc -q "read -c $aig; write ${aig%.*}_ref.v"
+    $abcprog -q "read -c $aig; write ${aig%.*}_ref.v"
     ../../yosys -qp "
 read_verilog ${aig%.*}_ref.v
 prep
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index d0537bb98..76acaa9cd 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -4,15 +4,17 @@ set -e
 
 OPTIND=1
 seed=""    # default to no seed specified
-while getopts "S:" opt
+abcopt=""
+while getopts "A:S:" opt
 do
     case "$opt" in
+	A) abcopt="-A $OPTARG" ;;
 	S) seed="-S $OPTARG" ;;
     esac
 done
 shift "$((OPTIND-1))"
 
-bash ../tools/autotest.sh $seed -G *.v
+bash ../tools/autotest.sh $abcopt $seed -G *.v
 
 for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 	echo -n "Testing expectations for $f .."
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 96d9cdda9..7b64b357f 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -23,12 +23,13 @@ warn_iverilog_git=false
 # The tests are skipped if firrtl2verilog is the empty string (the default).
 firrtl2verilog=""
 xfirrtl="../xfirrtl"
+abcprog="$toolsdir/../../yosys-abc"
 
 if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
 	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
@@ -65,6 +66,8 @@ while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
 			include_opts="$include_opts -I $OPTARG"
 			xinclude_opts="$xinclude_opts -i $OPTARG"
 			minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
+		A)
+			abcprog="$OPTARG" ;;
 		-)
 			case "${OPTARG}" in
 			    xfirrtl)
@@ -147,7 +150,7 @@ do
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
 		elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
-			"$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.${refext}"
+			$abcprog -c "read_aiger ../${fn}; write ${bn}_ref.${refext}"
 		else
 			refext=$ext
 			cp ../${fn} ${bn}_ref.${refext}

From fc87c010c504863b242b8882c1170396a7d1d43c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 14:18:56 -0700
Subject: [PATCH 04/30] autotest.sh to define _AUTOTB when test_autotb

---
 tests/tools/autotest.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 7b64b357f..4d3478628 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -157,7 +157,7 @@ do
 		fi
 
 		if [ ! -f ../${bn}_tb.v ]; then
-			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext}
+			"$toolsdir"/../../yosys -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext}
 		else
 			cp ../${bn}_tb.v ${bn}_tb.v
 		fi

From 7b298479d4a10ac20379955fa749e70560b72b7f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 2 Jul 2019 11:36:26 +0200
Subject: [PATCH 05/30] Fix read_verilog assert/assume/etc on default case
 label, fixes YosysHQ/SymbiYosys#53

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_lexer.l | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index d3fd91473..951d9c66f 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END
     to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some
     global state.. its a mess) */
 [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] {
+	if (!strcmp(yytext, "default"))
+		return TOK_DEFAULT;
 	frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 	return TOK_SVA_LABEL;
 }

From 4b49c0201edc37d0d3edd906e2693d6284a1b0ba Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 2 Jul 2019 16:47:54 +0100
Subject: [PATCH 06/30] Merge pull request #1153 from
 YosysHQ/dave/fix_multi_mux

memory_dff: Fix checking of feedback mux input when more than one mux
---
 passes/memory/memory_dff.cc   |  8 +++++---
 tests/memories/read_two_mux.v | 16 ++++++++++++++++
 tests/memories/run-test.sh    |  4 ++++
 3 files changed, 25 insertions(+), 3 deletions(-)
 create mode 100644 tests/memories/read_two_mux.v

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 5215cce44..32b97f27a 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -17,6 +17,7 @@
  *
  */
 
+#include <algorithm>
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 
@@ -183,12 +184,12 @@ struct MemoryDffWorker
 		if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data))
 		{
 			RTLIL::SigSpec en;
-			RTLIL::SigSpec check_q;
+			std::vector<RTLIL::SigSpec> check_q;
 
 			do {
 				bool enable_invert = mux_cells_a.count(sig_data) != 0;
 				Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
-				check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"));
+				check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")));
 				sig_data = sigmap(mux->getPort("\\Y"));
 				en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
 			} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
@@ -197,7 +198,8 @@ struct MemoryDffWorker
 				if (sigbit_users_count[bit] > 1)
 					goto skip_ff_after_read_merging;
 
-			if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q)
+			if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) &&
+					std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; }))
 			{
 				disconnect_dff(sig_data);
 				cell->setPort("\\CLK", clk_data);
diff --git a/tests/memories/read_two_mux.v b/tests/memories/read_two_mux.v
new file mode 100644
index 000000000..4f2e7e1cd
--- /dev/null
+++ b/tests/memories/read_two_mux.v
@@ -0,0 +1,16 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-no-rd-clk
+
+module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
+
+reg [7:0] bram[0:255];
+(* keep *) reg dummy;
+
+always @(posedge clk) begin
+	rdata <= re ? (reset ? 8'b0 : bram[addr]) : rdata;
+	if (we)
+		bram[addr] <= wdata;
+end
+
+endmodule
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index 76acaa9cd..8d1a8b413 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -31,6 +31,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 		grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected read clock."; false; }
 	fi
+	if grep -q expect-no-rd-clk $f; then
+		grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Expected no read clock."; false; }
+	fi
 	echo " ok."
 done
 

From d105e2f03f259e4f2be3d6d9ba970565d8422b87 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 3 Jul 2019 10:45:29 +0200
Subject: [PATCH 07/30] Merge pull request #1154 from
 whitequark/manual-sync-always

manual: explain the purpose of `sync always`
---
 manual/CHAPTER_Overview.tex | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 1a25c477f..3009bf2c0 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -331,8 +331,9 @@ to update {\tt \textbackslash{}q}.
 An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and
 exactly one RTLIL::CaseRule object, which is called the {\it root case}.
 
-An RTLIL::SyncRule object contains an (optional) synchronization condition
-(signal and edge-type) and zero or more assignments (RTLIL::SigSig).
+An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type) and zero or
+more assignments (RTLIL::SigSig). The {\tt always} synchronization condition is used to break combinatorial
+loops when a latch should be inferred instead.
 
 An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig)
 and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a

From fecd3aa2b15a20fc72d790b2437ee016ae879c14 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 3 Jul 2019 12:30:37 +0200
Subject: [PATCH 08/30] Merge pull request #1147 from YosysHQ/clifford/fix1144

Improve specify dummy parser
---
 frontends/verilog/verilog_parser.y | 95 +++++-------------------------
 tests/various/specify.v            | 11 +++-
 tests/various/specify.ys           |  2 +
 3 files changed, 26 insertions(+), 82 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index d89b2dc88..0fec445fa 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1021,13 +1021,8 @@ list_of_specparam_assignments:
 specparam_assignment:
 	ignspec_id '=' constant_mintypmax_expression ;
 
-/*
-pulsestyle_declaration :
-	;
-
-showcancelled_declaration :
-	;
-*/
+ignspec_opt_cond:
+	TOK_IF '(' ignspec_expr ')' | /* empty */;
 
 path_declaration :
 	simple_path_declaration ';'
@@ -1036,8 +1031,8 @@ path_declaration :
 	;
 
 simple_path_declaration :
-	parallel_path_description '=' path_delay_value |
-	full_path_description '=' path_delay_value
+	ignspec_opt_cond parallel_path_description '=' path_delay_value |
+	ignspec_opt_cond full_path_description '=' path_delay_value
 	;
 
 path_delay_value :
@@ -1047,32 +1042,20 @@ path_delay_value :
 	;
 
 list_of_path_delay_extra_expressions :
-/*
-	t_path_delay_expression
-	| trise_path_delay_expression ',' tfall_path_delay_expression
-	| trise_path_delay_expression ',' tfall_path_delay_expression ',' tz_path_delay_expression
-	| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
-	  tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression
-	| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
-	  tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression ','
-	  t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
-	  tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
-*/
-	',' path_delay_expression
-	|  ',' path_delay_expression ',' path_delay_expression
-	|  ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	|  ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	;
+	',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions;
+
+specify_edge_identifier :
+	TOK_POSEDGE | TOK_NEGEDGE ;
 
 parallel_path_description :
-	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
+	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
+	'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
+	'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
 
 full_path_description :
-	'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ;
+	'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
+	'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
+	'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
 
 // This was broken into 2 rules to solve shift/reduce conflicts
 list_of_path_inputs :
@@ -1112,56 +1095,6 @@ system_timing_args :
 	system_timing_arg |
 	system_timing_args ',' system_timing_arg ;
 
-/*
-t_path_delay_expression :
-	path_delay_expression;
-
-trise_path_delay_expression :
-	path_delay_expression;
-
-tfall_path_delay_expression :
-	path_delay_expression;
-
-tz_path_delay_expression :
-	path_delay_expression;
-
-t01_path_delay_expression :
-	path_delay_expression;
-
-t10_path_delay_expression :
-	path_delay_expression;
-
-t0z_path_delay_expression :
-	path_delay_expression;
-
-tz1_path_delay_expression :
-	path_delay_expression;
-
-t1z_path_delay_expression :
-	path_delay_expression;
-
-tz0_path_delay_expression :
-	path_delay_expression;
-
-t0x_path_delay_expression :
-	path_delay_expression;
-
-tx1_path_delay_expression :
-	path_delay_expression;
-
-t1x_path_delay_expression :
-	path_delay_expression;
-
-tx0_path_delay_expression :
-	path_delay_expression;
-
-txz_path_delay_expression :
-	path_delay_expression;
-
-tzx_path_delay_expression :
-	path_delay_expression;
-*/
-
 path_delay_expression :
 	ignspec_constant_expression;
 
diff --git a/tests/various/specify.v b/tests/various/specify.v
index afc421da8..5d44d78f7 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -7,9 +7,11 @@ module test (
 		if (EN) Q <= D;
 
 	specify
-		if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
+`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
+		if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
 		$setup(D, posedge CLK &&& EN, 5);
 		$hold(posedge CLK, D &&& EN, 6);
+`endif
 	endspecify
 endmodule
 
@@ -28,3 +30,10 @@ module test2 (
 		(B => Q) = 1.5;
 	endspecify
 endmodule
+
+module issue01144(input clk, d, output q);
+specify
+  (posedge clk => (q +: d)) = (3,1);
+  (posedge clk *> (q +: d)) = (3,1);
+endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index a5ca07219..00597e1e2 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -54,3 +54,5 @@ equiv_struct
 equiv_induct -seq 5
 equiv_status -assert
 design -reset
+
+read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v

From 17e0cc010c12fc69fdadc2c342da1ef8e16a2d91 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 5 Jul 2019 11:57:41 +0200
Subject: [PATCH 09/30] Merge pull request #1159 from
 btut/fix/1090_segfault_cell_and_wire

Throw runtime exception when trying to convert inexistend C++ object to Python
---
 misc/py_wrap_generator.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py
index 9e5727499..66d661fa1 100644
--- a/misc/py_wrap_generator.py
+++ b/misc/py_wrap_generator.py
@@ -779,6 +779,9 @@ class WClass:
 
 			#if self.link_type != link_types.pointer:
 			text += "\n\t\tstatic " + self.name + "* get_py_obj(" + long_name + "* ref)\n\t\t{"
+			text += "\n\t\t\tif(ref == nullptr){"
+			text += "\n\t\t\t\tthrow std::runtime_error(\"" + self.name + " does not exist.\");"
+			text += "\n\t\t\t}"
 			text += "\n\t\t\t" + self.name + "* ret = (" + self.name + "*)malloc(sizeof(" + self.name + "));"
 			if self.link_type == link_types.pointer:
 				text += "\n\t\t\tret->ref_obj = ref;"

From 76f20492a468ffef9902712e36c856f3a6e63dd5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 9 Jul 2019 16:56:29 +0200
Subject: [PATCH 10/30] Merge pull request #1162 from
 whitequark/rtlil-case-attrs

Allow attributes on individual switch cases in RTLIL
---
 backends/ilang/ilang_backend.cc |  5 +++++
 frontends/ilang/ilang_parser.y  | 13 +++++++++----
 kernel/rtlil.h                  |  2 +-
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index b4ba2b03f..313af7d5c 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -204,6 +204,11 @@ void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const
 
 	for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it)
 	{
+		for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) {
+			f << stringf("%s  attribute %s ", indent.c_str(), ait->first.c_str());
+			dump_const(f, ait->second);
+			f << stringf("\n");
+		}
 		f << stringf("%s  case ", indent.c_str());
 		for (size_t i = 0; i < (*it)->compare.size(); i++) {
 			if (i > 0)
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index 44c99906a..b4b9693da 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -282,14 +282,14 @@ proc_stmt:
 	} case_body sync_list TOK_END EOL;
 
 switch_stmt:
-	attr_list TOK_SWITCH sigspec EOL {
+	TOK_SWITCH sigspec EOL {
 		RTLIL::SwitchRule *rule = new RTLIL::SwitchRule;
-		rule->signal = *$3;
+		rule->signal = *$2;
 		rule->attributes = attrbuf;
 		switch_stack.back()->push_back(rule);
 		attrbuf.clear();
-		delete $3;
-	} switch_body TOK_END EOL;
+		delete $2;
+	} attr_list switch_body TOK_END EOL;
 
 attr_list:
 	/* empty */ |
@@ -298,9 +298,11 @@ attr_list:
 switch_body:
 	switch_body TOK_CASE {
 		RTLIL::CaseRule *rule = new RTLIL::CaseRule;
+		rule->attributes = attrbuf;
 		switch_stack.back()->back()->cases.push_back(rule);
 		switch_stack.push_back(&rule->switches);
 		case_stack.push_back(rule);
+		attrbuf.clear();
 	} compare_list EOL case_body {
 		switch_stack.pop_back();
 		case_stack.pop_back();
@@ -319,12 +321,15 @@ compare_list:
 	/* empty */;
 
 case_body:
+	case_body attr_stmt |
 	case_body switch_stmt |
 	case_body assign_stmt |
 	/* empty */;
 
 assign_stmt:
 	TOK_ASSIGN sigspec sigspec EOL {
+		if (attrbuf.size() != 0)
+			rtlil_frontend_ilang_yyerror("dangling attribute");
 		case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3));
 		delete $2;
 		delete $3;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 8509670ff..7b7367fba 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1315,7 +1315,7 @@ public:
 #endif
 };
 
-struct RTLIL::CaseRule
+struct RTLIL::CaseRule : public RTLIL::AttrObject
 {
 	std::vector<RTLIL::SigSpec> compare;
 	std::vector<RTLIL::SigSig> actions;

From 8af7ced5cd452bd0ef1e6bc17206e9360a893e49 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 9 Jul 2019 16:57:16 +0200
Subject: [PATCH 11/30] Merge pull request #1163 from
 whitequark/more-case-attrs

More support for case rule attributes
---
 backends/verilog/verilog_backend.cc | 17 +++++++++++------
 frontends/ast/genrtlil.cc           |  1 +
 passes/proc/proc_mux.cc             | 26 ++++++++++++++++----------
 3 files changed, 28 insertions(+), 16 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 827af5d85..6288502a5 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -364,20 +364,22 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 	}
 }
 
-void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false)
+void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false, bool as_comment = false)
 {
 	if (noattr)
 		return;
+	if (attr2comment)
+		as_comment = true;
 	for (auto it = attributes.begin(); it != attributes.end(); ++it) {
-		f << stringf("%s" "%s %s", indent.c_str(), attr2comment ? "/*" : "(*", id(it->first).c_str());
+		f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str());
 		f << stringf(" = ");
 		if (modattr && (it->second == Const(0, 1) || it->second == Const(0)))
 			f << stringf(" 0 ");
 		else if (modattr && (it->second == Const(1, 1) || it->second == Const(1)))
 			f << stringf(" 1 ");
 		else
-			dump_const(f, it->second, -1, 0, false, attr2comment);
-		f << stringf(" %s%c", attr2comment ? "*/" : "*)", term);
+			dump_const(f, it->second, -1, 0, false, as_comment);
+		f << stringf(" %s%c", as_comment ? "*/" : "*)", term);
 	}
 }
 
@@ -1492,6 +1494,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 		return;
 	}
 
+	dump_attributes(f, indent, sw->attributes);
 	f << stringf("%s" "casez (", indent.c_str());
 	dump_sigspec(f, sw->signal);
 	f << stringf(")\n");
@@ -1511,7 +1514,9 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 				dump_sigspec(f, (*it)->compare[i]);
 			}
 		}
-		f << stringf(":\n");
+		f << stringf(":");
+		dump_attributes(f, indent, (*it)->attributes, ' ', /*modattr=*/false, /*as_comment=*/true);
+		f << stringf("\n");
 		dump_case_body(f, indent + "    ", *it);
 	}
 
@@ -1662,7 +1667,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		}
 	}
 
-	dump_attributes(f, indent, module->attributes, '\n', true);
+	dump_attributes(f, indent, module->attributes, '\n', /*attr2comment=*/true);
 	f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
 	bool keep_running = true;
 	for (int port_id = 1; keep_running; port_id++) {
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 079fc11e5..571ddd988 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -504,6 +504,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 					RTLIL::CaseRule *backup_case = current_case;
 					current_case = new RTLIL::CaseRule;
+					current_case->attributes["\\src"] = stringf("%s:%d", child->filename.c_str(), child->linenum);
 					last_generated_case = current_case;
 					addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
 					for (auto node : child->children) {
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index aac0b121c..d029282fd 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -144,7 +144,13 @@ struct SnippetSwCache
 	}
 };
 
-RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, bool ifxmode)
+void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs)
+{
+	cell->attributes = sw->attributes;
+	cell->add_strpool_attribute("\\src", cs->get_strpool_attribute("\\src"));
+}
+
+RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
 {
 	std::stringstream sstr;
 	sstr << "$procmux$" << (autoidx++);
@@ -173,7 +179,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 		{
 			// create compare cell
 			RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? "$eqx" : "$eq");
-			eq_cell->attributes = sw->attributes;
+			apply_attrs(eq_cell, sw, cs);
 
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0);
@@ -199,7 +205,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 
 		// reduce cmp vector to one logic signal
 		RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or");
-		any_cell->attributes = sw->attributes;
+		apply_attrs(any_cell, sw, cs);
 
 		any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 		any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
@@ -212,7 +218,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 	return RTLIL::SigSpec(ctrl_wire);
 }
 
-RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, bool ifxmode)
+RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
 {
 	log_assert(when_signal.size() == else_signal.size());
 
@@ -224,7 +230,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 		return when_signal;
 
 	// compare results
-	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, ifxmode);
+	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
 	if (ctrl_sig.size() == 0)
 		return when_signal;
 	log_assert(ctrl_sig.size() == 1);
@@ -234,7 +240,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 
 	// create the multiplexer itself
 	RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux");
-	mux_cell->attributes = sw->attributes;
+	apply_attrs(mux_cell, sw, cs);
 
 	mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
 	mux_cell->setPort("\\A", else_signal);
@@ -246,7 +252,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 	return RTLIL::SigSpec(result_wire);
 }
 
-void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, bool ifxmode)
+void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
 {
 	log_assert(last_mux_cell != NULL);
 	log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size());
@@ -254,7 +260,7 @@ void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::ve
 	if (when_signal == last_mux_cell->getPort("\\A"))
 		return;
 
-	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, ifxmode);
+	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
 	log_assert(ctrl_sig.size() == 1);
 	last_mux_cell->type = "$pmux";
 
@@ -395,9 +401,9 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
 			RTLIL::CaseRule *cs2 = sw->cases[case_idx];
 			RTLIL::SigSpec value = signal_to_mux_tree(mod, swcache, swpara, cs2, sig, initial_val, ifxmode);
 			if (last_mux_cell && pgroups[case_idx] == pgroups[case_idx+1])
-				append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, ifxmode);
+				append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, cs2, ifxmode);
 			else
-				result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, ifxmode);
+				result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, cs2, ifxmode);
 		}
 	}
 

From c8979a3353c531884fd7f7dec8c06682d0b4b3ec Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 9 Jul 2019 18:51:23 +0100
Subject: [PATCH 12/30] Update CHANGELOG

Signed-off-by: David Shah <dave@ds0.me>
---
 CHANGELOG | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG b/CHANGELOG
index 03ab2a7cc..b3a697562 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -28,6 +28,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "synth_ecp5 -nowidelut"
     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
+    - Added support for attributes on case rules
 
 
 Yosys 0.7 .. Yosys 0.8

From 1d58bbb79c36d88c24008797947789d9ae5605be Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 9 Jul 2019 22:51:25 +0200
Subject: [PATCH 13/30] Merge pull request #1175 from
 whitequark/write_verilog-fix-case-attr-position

write_verilog: fix placement of case attributes
---
 backends/verilog/verilog_backend.cc | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6288502a5..087c6fec6 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1501,6 +1501,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 
 	bool got_default = false;
 	for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
+		dump_attributes(f, indent + "  ", (*it)->attributes, '\n', /*modattr=*/false, /*as_comment=*/true);
 		if ((*it)->compare.size() == 0) {
 			if (got_default)
 				continue;
@@ -1514,9 +1515,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 				dump_sigspec(f, (*it)->compare[i]);
 			}
 		}
-		f << stringf(":");
-		dump_attributes(f, indent, (*it)->attributes, ' ', /*modattr=*/false, /*as_comment=*/true);
-		f << stringf("\n");
+		f << stringf(":\n");
 		dump_case_body(f, indent + "    ", *it);
 	}
 

From 82a29720684dc8db452289321340bf6e78dcbd2c Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 26 Jul 2019 16:45:51 +0100
Subject: [PATCH 14/30] Update CHANGELOG

Signed-off-by: David Shah <dave@ds0.me>
---
 CHANGELOG | 111 +++++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 101 insertions(+), 10 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index b3a697562..afbcffa26 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,33 +3,124 @@ List of major changes and improvements between releases
 =======================================================
 
 
-Yosys 0.8 .. Yosys 0.8-dev
+Yosys 0.8 .. Yosys 0.9
 --------------------------
 
  * Various
-    - Added $changed support to read_verilog
+    - Many bugfixes and small improvements
+    - Added support for SystemVerilog interfaces and modports
     - Added "write_edif -attrprop"
-    - Added "ice40_unlut" pass
     - Added "opt_lut" pass
-    - Added "synth_ice40 -relut"
-    - Added "synth_ice40 -noabc"
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
-    - Added "shregmap -tech xilinx"
+    - Added "flowmap" LUT mapping pass
+    - Added "rename -wire" to rename cells based on the wires they drive
+    - Added "bugpoint" for creating minimised testcases
+    - Added "write_edif -gndvccy"
+    - "write_verilog" to escape Verilog keywords
+    - Fixed sign handling of real constants
+    - "write_verilog" to write initial statement for initial flop state
+    - Added pmgen pattern matcher generator
+    - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
+    - Added "setundef -params" to replace undefined cell parameters
+    - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
+    - Fixed handling of defparam when default_nettype is none
+    - Fixed "wreduce" flipflop handling
+    - Fixed FIRRTL to Verilog process instance subfield assignment
+    - Added "write_verilog -siminit"
+    - Several fixes and improvements for mem2reg memories
+    - Fixed handling of task output ports in clocked always blocks
+    - Improved handling of and-with-1 and or-with-0 in "opt_expr"
     - Added "read_aiger" frontend
+    - Added "mutate" pass
+    - Added "hdlname" attribute
+    - Added "rename -output"
+    - Added "read_ilang -lib"
+    - Improved "proc" full_case detection and handling
+    - Added "whitebox" and "lib_whitebox" attributes
+    - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
+    - Added Python bindings and support for Python plug-ins
+    - Added "pmux2shiftx"
+    - Added log_debug framework for reduced default verbosity
+    - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
+    - Added "peepopt" peephole optimisation pass using pmgen
+    - Added approximate support for SystemVerilog "var" keyword
+    - Added parsing of "specify" blocks into $specrule and $specify[23]
+    - Added support for attributes on parameters and localparams
+    - Added support for parsing attributes on port connections
+    - Added "wreduce -keepdc"
+    - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
+    - Added Verilog wand/wor wire type support
+    - Added support for elaboration system tasks
     - Added "muxcover -mux{4,8,16}=<cost>"
     - Added "muxcover -dmux=<cost>"
     - Added "muxcover -nopartial"
     - Added "muxpack" pass
     - Added "pmux2shiftx -norange"
+    - Added support for "~" in filename parsing
+    - Added "read_verilog -pwires" feature to turn parameters into wires
+    - Fixed sign extension of unsized constants with 'bx and 'bz MSB
+    - Fixed genvar to be a signed type
+    - Added support for attributes on case rules
+    - Added "upto" and "offset" to JSON frontend and backend
+    - Several liberty file parser improvements
+    - Fixed handling of more complex BRAM patterns
+    - Add "write_aiger -I -O -B"
+
+ * Formal Verification
+    - Added $changed support to read_verilog
+    - Added "read_verilog -noassert -noassume -assert-assumes"
+    - Added btor ops for $mul, $div, $mod and $concat
+    - Added yosys-smtbmc support for btor witnesses
+    - Added "supercover" pass
+    - Fixed $global_clock handling vs autowire
+    - Added $dffsr support to "async2sync"
+    - Added "fmcombine" pass
+    - Added memory init support in "write_btor"
+    - Added "cutpoint" pass
+    - Changed "ne" to "neq" in btor2 output
+    - Added support for SVA "final" keyword
+    - Added "fmcombine -initeq -anyeq"
+    - Added timescale and generated-by header to yosys-smtbmc vcd output
+    - Improved BTOR2 handling of undriven wires
+
+ * Verific support
+    - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
+    - Improved support for asymmetric memories
+    - Added "verific -chparam"
+    - Fixed "verific -extnets" for more complex situations
+    - Added "read -verific" and "read -noverific"
+    - Added "hierarchy -chparam"
+
+ * New back-ends
+    - Added initial Anlogic support
+    - Added initial SmartFusion2 and IGLOO2 support
+
+ * ECP5 support
+    - Added "synth_ecp5 -nowidelut"
+    - Added BRAM inference support to "synth_ecp5"
+    - Added support for transforming Diamond IO and flipflop primitives
+
+ * iCE40 support
+    - Added "ice40_unlut" pass
+    - Added "synth_ice40 -relut"
+    - Added "synth_ice40 -noabc"
+    - Added "synth_ice40 -dffe_min_ce_use"
+    - Added DSP inference support using pmgen
+    - Added support for initialising BRAM primitives from a file
+    - Added iCE40 Ultra RGB LED driver cells
+
+ * Xilinx support 
+    - Use "write_edif -pvector bra" for Xilinx EDIF files
+    - Fixes for VPR place and route support with "synth_xilinx"
+    - Added more cell simulation models
+    - Added "synth_xilinx -family"
+    - Added "stat -tech xilinx" to estimate logic cell usage
     - Added "synth_xilinx -nocarry"
     - Added "synth_xilinx -nowidelut"
-    - Added "synth_ecp5 -nowidelut"
     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
-    - Fixed sign extension of unsized constants with 'bx and 'bz MSB
-    - Added support for attributes on case rules
-
+    - Added support for mapping RAM32X1D
 
 Yosys 0.7 .. Yosys 0.8
 ----------------------

From e9c5f1b3467d4566978dfb07c3b1fa91e94ef761 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 31 Jul 2019 11:49:48 +0200
Subject: [PATCH 15/30] Fix formatting for msys2 mingw build using GetSize

---
 Makefile                                   |  2 ++
 misc/launcher.c                            |  3 ++-
 passes/opt/opt_lut.cc                      |  8 ++++----
 passes/opt/rmports.cc                      |  2 +-
 passes/techmap/flowmap.cc                  | 10 +++++-----
 techlibs/anlogic/anlogic_determine_init.cc |  4 ++--
 techlibs/anlogic/anlogic_eqn.cc            |  4 ++--
 techlibs/gowin/determine_init.cc           |  4 ++--
 8 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/Makefile b/Makefile
index bbae8c159..d3b5b8fa6 100644
--- a/Makefile
+++ b/Makefile
@@ -861,9 +861,11 @@ config-mxe: clean
 
 config-msys2: clean
 	echo 'CONFIG := msys2' > Makefile.conf
+	echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
 
 config-msys2-64: clean
 	echo 'CONFIG := msys2-64' > Makefile.conf
+	echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
 
 config-cygwin: clean
 	echo 'CONFIG := cygwin' > Makefile.conf
diff --git a/misc/launcher.c b/misc/launcher.c
index 157d68cf3..e0d8208f1 100644
--- a/misc/launcher.c
+++ b/misc/launcher.c
@@ -61,6 +61,7 @@ SOFTWARE. */
 #include <windows.h>
 #include <tchar.h>
 #include <fcntl.h>
+#include <unistd.h>
 
 int child_pid=0;
 
@@ -338,7 +339,7 @@ int run(int argc, char **argv, int is_gui) {
 
     if (is_gui) {
         /* Use exec, we don't need to wait for the GUI to finish */
-        execv(ptr, (const char * const *)(newargs));
+        execv(ptr, (char * const *)(newargs));
         return fail("Could not exec %s", ptr);   /* shouldn't get here! */
     }
 
diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 26855fd70..dda10ec17 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -81,7 +81,7 @@ struct OptLutWorker
 			}
 		}
 
-		log("Number of LUTs: %8zu\n", luts.size());
+		log("Number of LUTs: %8d\n", GetSize(luts));
 		for (int arity = 1; arity <= max_arity; arity++)
 		{
 			if (arity_counts[arity])
@@ -353,14 +353,14 @@ struct OptLutWorker
 
 					int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
 					if (lutA_dlogic_inputs.size())
-						log("  Cell A is a %d-LUT with %zu dedicated connections. ", lutA_arity, lutA_dlogic_inputs.size());
+						log("  Cell A is a %d-LUT with %d dedicated connections. ", lutA_arity, GetSize(lutA_dlogic_inputs));
 					else
 						log("  Cell A is a %d-LUT. ", lutA_arity);
 					if (lutB_dlogic_inputs.size())
-						log("Cell B is a %d-LUT with %zu dedicated connections.\n", lutB_arity, lutB_dlogic_inputs.size());
+						log("Cell B is a %d-LUT with %d dedicated connections.\n", lutB_arity, GetSize(lutB_dlogic_inputs));
 					else
 						log("Cell B is a %d-LUT.\n", lutB_arity);
-					log("  Cells share %zu input(s) and can be merged into one %d-LUT.\n", common_inputs.size(), lutM_arity);
+					log("  Cells share %d input(s) and can be merged into one %d-LUT.\n", GetSize(common_inputs), lutM_arity);
 
 					const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B;
 					int combine_mask = 0;
diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc
index fc1596ebf..32363dd68 100644
--- a/passes/opt/rmports.cc
+++ b/passes/opt/rmports.cc
@@ -171,7 +171,7 @@ struct RmportsPassPass : public Pass {
 			wire->port_output = false;
 			wire->port_id = 0;
 		}
-		log("Removed %zu unused ports.\n", unused_ports.size());
+		log("Removed %d unused ports.\n", GetSize(unused_ports));
 
 		// Re-number all of the wires that DO have ports still on them
 		for(size_t i=0; i<module->ports.size(); i++)
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index f5892a60e..96d0df5f8 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -783,7 +783,7 @@ struct FlowmapWorker
 		int depth = 0;
 		for (auto label : labels)
 			depth = max(depth, label.second);
-		log("Mapped to %zu LUTs with maximum depth %d.\n", lut_nodes.size(), depth);
+		log("Mapped to %d LUTs with maximum depth %d.\n", GetSize(lut_nodes), depth);
 
 		if (debug)
 		{
@@ -1195,7 +1195,7 @@ struct FlowmapWorker
 
 	bool relax_depth_for_bound(bool first, int depth_bound, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs)
 	{
-		size_t initial_count = lut_nodes.size();
+		int initial_count = GetSize(lut_nodes);
 
 		for (auto node : lut_nodes)
 		{
@@ -1215,7 +1215,7 @@ struct FlowmapWorker
 
 			if (potentials.empty())
 			{
-				log("  Relaxed to %zu (+%zu) LUTs.\n", lut_nodes.size(), lut_nodes.size() - initial_count);
+				log("  Relaxed to %d (+%d) LUTs.\n", GetSize(lut_nodes), GetSize(lut_nodes) - initial_count);
 				if (!first && break_num == 1)
 				{
 					log("  Design fully relaxed.\n");
@@ -1419,9 +1419,9 @@ struct FlowmapWorker
 			lut_area += lut_table.size();
 
 			if ((int)input_nodes.size() >= minlut)
-				log("  Packed into a %zu-LUT %s.%s.\n", input_nodes.size(), log_id(module), log_id(lut));
+				log("  Packed into a %d-LUT %s.%s.\n", GetSize(input_nodes), log_id(module), log_id(lut));
 			else
-				log("  Packed into a %zu-LUT %s.%s (implemented as %d-LUT).\n", input_nodes.size(), log_id(module), log_id(lut), minlut);
+				log("  Packed into a %d-LUT %s.%s (implemented as %d-LUT).\n", GetSize(input_nodes), log_id(module), log_id(lut), minlut);
 		}
 
 		for (auto node : mapped_nodes)
diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc
index 34b1d4f8a..c4089dac2 100644
--- a/techlibs/anlogic/anlogic_determine_init.cc
+++ b/techlibs/anlogic/anlogic_determine_init.cc
@@ -50,7 +50,7 @@ struct AnlogicDetermineInitPass : public Pass {
 
 		extra_args(args, args.size(), design);
 
-		size_t cnt = 0;
+		int cnt = 0;
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct AnlogicDetermineInitPass : public Pass {
 				}
 			}
 		}
-		log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+		log_header(design, "Updated %d cells with determined init value.\n", cnt);
 	}
 } AnlogicDetermineInitPass;
 
diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc
index 741bf04cc..070d39a20 100644
--- a/techlibs/anlogic/anlogic_eqn.cc
+++ b/techlibs/anlogic/anlogic_eqn.cc
@@ -69,7 +69,7 @@ struct AnlogicEqnPass : public Pass {
 
 		extra_args(args, args.size(), design);
 
-		size_t cnt = 0;
+		int cnt = 0;
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
@@ -106,7 +106,7 @@ struct AnlogicEqnPass : public Pass {
 				}
 			}
 		}
-		log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt);
+		log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt);
 	}
 } AnlogicEqnPass;
 
diff --git a/techlibs/gowin/determine_init.cc b/techlibs/gowin/determine_init.cc
index 991e5245a..d9a0880f6 100644
--- a/techlibs/gowin/determine_init.cc
+++ b/techlibs/gowin/determine_init.cc
@@ -50,7 +50,7 @@ struct DetermineInitPass : public Pass {
 
 		extra_args(args, args.size(), design);
 
-		size_t cnt = 0;
+		int cnt = 0;
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct DetermineInitPass : public Pass {
 				}
 			}
 		}
-		log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+		log_header(design, "Updated %d cells with determined init value.\n", cnt);
 	}
 } DetermineInitPass;
 

From bf59f31b4366e2e595821dc9b35f6082ff0d747c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 31 Jul 2019 17:30:48 +0200
Subject: [PATCH 16/30] New mxe hacks needed to support 2ca237e

---
 kernel/yosys.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/kernel/yosys.h b/kernel/yosys.h
index c7b671724..730efe825 100644
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -87,6 +87,10 @@ extern int Tcl_EvalFile(Tcl_Interp *interp, const char *fileName);
 extern void Tcl_Finalize(void);
 extern int Tcl_GetCommandInfo(Tcl_Interp *interp, const char *cmdName, Tcl_CmdInfo *infoPtr);
 extern const char *Tcl_GetStringResult(Tcl_Interp *interp);
+extern Tcl_Obj *Tcl_NewStringObj(const char *bytes, int length);
+extern Tcl_Obj *Tcl_NewIntObj(int intValue);
+extern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]);
+extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags);
 #  endif
 #endif
 

From ce0de937f4036e70b18afd765428288596fa0200 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 31 Jul 2019 17:31:07 +0200
Subject: [PATCH 17/30] Fix yosys linking for mxe

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index d3b5b8fa6..579fff007 100644
--- a/Makefile
+++ b/Makefile
@@ -394,7 +394,7 @@ endif
 
 ifeq ($(CONFIG),mxe)
 CXXFLAGS += -DYOSYS_ENABLE_TCL
-LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 -lz
+LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 -lz -luserenv
 else
 CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags tcl || echo -I$(TCL_INCLUDE)) -DYOSYS_ENABLE_TCL
 ifeq ($(OS), FreeBSD)

From 2ec5a3ec9248e86bb24f29253f1610aeff431e7d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 31 Jul 2019 18:02:27 +0200
Subject: [PATCH 18/30] Fix linking issue for new mxe and pthread

---
 Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 579fff007..89155fae8 100644
--- a/Makefile
+++ b/Makefile
@@ -260,7 +260,8 @@ CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
 LDLIBS := $(filter-out -lrt,$(LDLIBS))
 ABCMKARGS += ARCHFLAGS="-DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
-ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc"
+# TODO: Try to solve pthread linking issue in more appropriate way
+ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" LDFLAGS="-Wl,--allow-multiple-definition" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc"
 EXE = .exe
 
 else ifeq ($(CONFIG),msys2)

From 2b4e50ac3dd33ddf978eb4994985727338c61dff Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 31 Jul 2019 09:10:24 +0200
Subject: [PATCH 19/30] Visual Studio build fix

---
 passes/techmap/abc.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 5b19d84fb..bf05c68e7 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -49,6 +49,7 @@
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
+#include <cctype>
 #include <cerrno>
 #include <sstream>
 #include <climits>

From 5e0f6c9ae58a91e7ef631ee67dd494e22fd784f0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 22 Aug 2019 18:43:16 +0200
Subject: [PATCH 20/30] Bump year in copyright notice

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 COPYING         | 2 +-
 README.md       | 2 +-
 kernel/yosys.cc | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/COPYING b/COPYING
index a121cdfe9..0839088c3 100644
--- a/COPYING
+++ b/COPYING
@@ -1,4 +1,4 @@
-Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>
+Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>
 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
diff --git a/README.md b/README.md
index 42f972c8e..83167bfee 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 ```
 yosys -- Yosys Open SYnthesis Suite
 
-Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>
+Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>
 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 94d6d675f..69a141768 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -129,7 +129,7 @@ void yosys_banner()
 	log(" |                                                                            |\n");
 	log(" |  yosys -- Yosys Open SYnthesis Suite                                       |\n");
 	log(" |                                                                            |\n");
-	log(" |  Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>           |\n");
+	log(" |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |\n");
 	log(" |                                                                            |\n");
 	log(" |  Permission to use, copy, modify, and/or distribute this software for any  |\n");
 	log(" |  purpose with or without fee is hereby granted, provided that the above    |\n");

From 68e673d687e18ec8e18555cda0a0d83ca2afc84d Mon Sep 17 00:00:00 2001
From: Chris Shucksmith <chris@bitmex.com>
Date: Thu, 22 Aug 2019 16:37:40 +0100
Subject: [PATCH 21/30] require tcl-tk in Brewfile

---
 Brewfile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Brewfile b/Brewfile
index 0c58ce161..4ffe50e86 100644
--- a/Brewfile
+++ b/Brewfile
@@ -6,3 +6,4 @@ brew "git"
 brew "graphviz"
 brew "pkg-config"
 brew "python3"
+brew "tcl-tk"

From 7fafaa896dc16e83347ab33cc649da1f8e8033b7 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 22 Aug 2019 20:43:52 +0200
Subject: [PATCH 22/30] do not require boost if pyosys is not used

---
 Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Makefile b/Makefile
index 89155fae8..21f1c5f46 100644
--- a/Makefile
+++ b/Makefile
@@ -90,8 +90,10 @@ PLUGIN_LDFLAGS += -undefined dynamic_lookup
 ifneq ($(shell which brew),)
 BREW_PREFIX := $(shell brew --prefix)/opt
 $(info $$BREW_PREFIX is [${BREW_PREFIX}])
+ifeq ($(ENABLE_PYOSYS),1)
 CXXFLAGS += -I$(BREW_PREFIX)/boost/include/boost
 LDFLAGS += -L$(BREW_PREFIX)/boost/lib
+endif
 CXXFLAGS += -I$(BREW_PREFIX)/readline/include
 LDFLAGS += -L$(BREW_PREFIX)/readline/lib
 PKG_CONFIG_PATH := $(BREW_PREFIX)/libffi/lib/pkgconfig:$(PKG_CONFIG_PATH)

From 55aa444e059fb011f0af7293845178dec2ef4a50 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 23 Aug 2019 10:37:50 +0200
Subject: [PATCH 23/30] Make macOS depenency clear

---
 README.md | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 83167bfee..5132332a5 100644
--- a/README.md
+++ b/README.md
@@ -69,11 +69,14 @@ prerequisites for building yosys:
 		graphviz xdot pkg-config python3 libboost-system-dev \
 		libboost-python-dev libboost-filesystem-dev
 
-Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
+Similarily, on Mac OS X Homebrew can be used to install dependencies:
 
 	$ brew tap Homebrew/bundle && brew bundle
+
+or MacPorts:
+
 	$ sudo port install bison flex readline gawk libffi \
-		git graphviz pkgconfig python36 boost
+		git graphviz pkgconfig python36 boost tcl
 
 On FreeBSD use the following command to install all prerequisites:
 

From 43927e5910f54b41530dd4dbba8059b2c80d8c26 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 11:26:32 -0700
Subject: [PATCH 24/30] Bump gcc from 4.8 to 4.9 as undefined reference

... to `__warn_memset_zero_len'.
Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
---
 .travis.yml | 42 +++++++-----------------------------------
 1 file changed, 7 insertions(+), 35 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 957735f1d..a4e9ffe40 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -18,7 +18,7 @@ matrix:
       addons:
         apt:
           packages:
-            - g++-4.8
+            - g++-4.9
             - gperf
             - build-essential
             - bison
@@ -37,35 +37,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8"
-
-    # Latest gcc-6 on Travis Linux
-    - os: linux
-      addons:
-        apt:
-          sources:
-            - ubuntu-toolchain-r-test
-          packages:
-            - g++-6
-            - gperf
-            - build-essential
-            - bison
-            - flex
-            - libreadline-dev
-            - gawk
-            - tcl-dev
-            - libffi-dev
-            - git
-            - graphviz
-            - xdot
-            - pkg-config
-            - python
-            - python3
-            - libboost-system-dev
-            - libboost-python-dev
-            - libboost-filesystem-dev
-      env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-6 && CXX=g++-6"
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9"
 
     # Latest gcc supported on Travis Linux
     - os: linux
@@ -74,7 +46,7 @@ matrix:
           sources:
             - ubuntu-toolchain-r-test
           packages:
-            - g++-7
+            - g++-9
             - gperf
             - build-essential
             - bison
@@ -93,7 +65,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-7 && CXX=g++-7"
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-9 && CXX=g++-9"
 
     # Clang which ships on Trusty Linux
     - os: linux
@@ -129,9 +101,9 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-trusty-5.0
+            - llvm-toolchain-bionic-8.0
           packages:
-            - clang-5.0
+            - clang-8.0
             - gperf
             - build-essential
             - bison
@@ -150,7 +122,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=clang && CC=clang-5.0 && CXX=clang++-5.0"
+        - MATRIX_EVAL="CONFIG=clang && CC=clang-8.0 && CXX=clang++-8.0"
 
 #   # Latest clang on Mac OS X
 #   - os: osx

From bf40f2f895ab5a5ebe047e9281d5ba8707e04e94 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 11:52:08 -0700
Subject: [PATCH 25/30] bionic -> xenial as its on whitelist

---
 .travis.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.travis.yml b/.travis.yml
index a4e9ffe40..bc07c741e 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -101,7 +101,7 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-bionic-8.0
+            - llvm-toolchain-xenial-8
           packages:
             - clang-8.0
             - gperf

From fdc438e551f5ee13a62e216b861237b2195d9131 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 12:16:02 -0700
Subject: [PATCH 26/30] Bump to gcc-5 as `__warn_memset_zero_len' symbol not in
 16.04!?!

---
 .travis.yml | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index bc07c741e..093dd2dbf 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -13,12 +13,14 @@ env:
 
 matrix:
   include:
-    # Latest gcc-4.8, earliest version supported by Travis
+    # Earliest gcc version that works
+    #   4.8 and 4.9 fails to compile iverilog giving:
+    #   "undefined reference to `__warn_memset_zero_len'"
     - os: linux
       addons:
         apt:
           packages:
-            - g++-4.9
+            - g++-5
             - gperf
             - build-essential
             - bison
@@ -37,7 +39,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9"
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-5 && CXX=g++-5"
 
     # Latest gcc supported on Travis Linux
     - os: linux

From fcb102d60e7a6295fd78214917df2a15834808d0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 12:23:15 -0700
Subject: [PATCH 27/30] Remove .0 from clang-8.0

---
 .travis.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 093dd2dbf..c5fe244fb 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -105,7 +105,7 @@ matrix:
           sources:
             - llvm-toolchain-xenial-8
           packages:
-            - clang-8.0
+            - clang-8
             - gperf
             - build-essential
             - bison
@@ -124,7 +124,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=clang && CC=clang-8.0 && CXX=clang++-8.0"
+        - MATRIX_EVAL="CONFIG=clang && CC=clang-8 && CXX=clang++-8"
 
 #   # Latest clang on Mac OS X
 #   - os: osx

From b3dc28cf65dcadd9038ff068be239e2f81f504f4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 12:26:45 -0700
Subject: [PATCH 28/30] Revert "Bump to gcc-5 as `__warn_memset_zero_len'
 symbol not in 16.04!?!"

This reverts commit c82b2fa31f8965be2680c87af6cd9ac5d26ead4d.
---
 .travis.yml | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index c5fe244fb..61ade0e7a 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -13,14 +13,12 @@ env:
 
 matrix:
   include:
-    # Earliest gcc version that works
-    #   4.8 and 4.9 fails to compile iverilog giving:
-    #   "undefined reference to `__warn_memset_zero_len'"
+    # Latest gcc-4.8, earliest version supported by Travis
     - os: linux
       addons:
         apt:
           packages:
-            - g++-5
+            - g++-4.9
             - gperf
             - build-essential
             - bison
@@ -39,7 +37,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-5 && CXX=g++-5"
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9"
 
     # Latest gcc supported on Travis Linux
     - os: linux

From 4a4e28b55eb24ec4e83b092bf8478bb8149669c0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 12:28:17 -0700
Subject: [PATCH 29/30] Revert earliest to gcc-4.8, compile iverilog with
 default compiler

---
 .travis.yml      | 4 ++--
 .travis/setup.sh | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 61ade0e7a..c253b2ff7 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -18,7 +18,7 @@ matrix:
       addons:
         apt:
           packages:
-            - g++-4.9
+            - g++-4.8
             - gperf
             - build-essential
             - bison
@@ -37,7 +37,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9"
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8"
 
     # Latest gcc supported on Travis Linux
     - os: linux
diff --git a/.travis/setup.sh b/.travis/setup.sh
index 4af0b8ee9..02879b974 100755
--- a/.travis/setup.sh
+++ b/.travis/setup.sh
@@ -51,7 +51,7 @@ fi
 		git clone git://github.com/steveicarus/iverilog.git
 		cd iverilog
 		autoconf
-		./configure --prefix=$HOME/.local-bin
+		CC=gcc CXX=g++ ./configure --prefix=$HOME/.local-bin
 		make
 		make install
 		echo

From 1979e0b1f2482dbf0562f5116ab444280a377773 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 26 Aug 2019 10:37:53 +0200
Subject: [PATCH 30/30] Yosys 0.9

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 21f1c5f46..a67315415 100644
--- a/Makefile
+++ b/Makefile
@@ -114,7 +114,7 @@ LDFLAGS += -rdynamic
 LDLIBS += -lrt
 endif
 
-YOSYS_VER := 0.8+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 4d4665b.. 2> /dev/null | wc -l; })
+YOSYS_VER := 0.9
 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o