Add missing items in CHANGELOG

2021-10-29 13:31:41 +02:00 · 2021-10-29 13:31:41 +02:00 · c0edfa8788
parent 55f07fe56f
commit c0edfa8788
1 changed files with 6 additions and 0 deletions
--- a/6
+++ b/6
@ -16,6 +16,12 @@ Yosys 0.10 .. Yosys 0.10-dev
    - Fixed an issue where connecting a slice covering the entirety of a signed
      signal to a cell input would cause a failed assertion

+ * Verific support
+    - Importer support for {PRIM,WIDE_OPER}_DFF
+    - Importer support for PRIM_BUFIF1
+    - Option to use Verific without VHDL support
+    - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
+
 Yosys 0.9 .. Yosys 0.10
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