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Add CHANGELOG entry

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Eddie Hung 2019-08-22 11:22:53 -07:00
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commit 7a9031c48e
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@ -27,6 +27,8 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "opt_share" pass, run as part of "opt -full"
- Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
- Removed "ice40_unlut"
- Added "xilinx_srl" for Xilinx shift register extraction
- Removed "shregmap -tech xilinx"
Yosys 0.8 .. Yosys 0.8-dev
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