mirror of https://github.com/YosysHQ/yosys.git
Add CHANGELOG entry
This commit is contained in:
parent
36d94caec1
commit
7a9031c48e
|
@ -27,6 +27,8 @@ Yosys 0.9 .. Yosys 0.9-dev
|
|||
- Added "opt_share" pass, run as part of "opt -full"
|
||||
- Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
|
||||
- Removed "ice40_unlut"
|
||||
- Added "xilinx_srl" for Xilinx shift register extraction
|
||||
- Removed "shregmap -tech xilinx"
|
||||
|
||||
Yosys 0.8 .. Yosys 0.8-dev
|
||||
--------------------------
|
||||
|
|
Loading…
Reference in New Issue