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Upadte documentation and changelog
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Miodrag Milanovic
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15
CHANGELOG
15
CHANGELOG
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@ -4,6 +4,21 @@ List of major changes and improvements between releases
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Yosys 0.18 .. Yosys 0.18-dev
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--------------------------
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* Various
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- Added support for $pos cell in btor backend
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* New commands and options
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- Added option "-rom-only" to "memory_libmap" pass
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- Added option "-smtcheck" to "hierarchy" pass
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- Added option "-keepdc" to "memory_libmap" pass
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- Added option "-suffix" to "rename" pass
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- Added "gatemate_foldinv" pass
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* GateMate support
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- Added LUT tree mapping
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* Verific support
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- Added option "-pp" to "verific -import"
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Yosys 0.17 .. Yosys 0.18
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--------------------------
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@ -2496,6 +2496,7 @@ struct VerificPass : public Pass {
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log("\n");
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log(" -v, -vv\n");
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log(" Verbose log messages. (-vv is even more verbose than -v.)\n");
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log("\n");
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log(" -pp <filename>\n");
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log(" Pretty print design after elaboration to specified file.\n");
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log("\n");
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@ -2256,6 +2256,16 @@ and simulus signal from FST file
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number of clock cycles to simulate (default: 20)
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\end{lstlisting}
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\section{gatemate\_foldinv -- fold inverters into Gatemate LUT trees}
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\label{cmd:gatemate_foldinv}
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\begin{lstlisting}[numbers=left,frame=single]
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gatemate_foldinv [selection]
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This pass searches for $__CC_NOT cells and folds them into CC_LUT2, CC_L2T4
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and CC_L2T5 cells as created by LUT tree mapping.
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\end{lstlisting}
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\section{glift -- create GLIFT models and optimization problems}
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\label{cmd:glift}
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\begin{lstlisting}[numbers=left,frame=single]
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@ -2950,6 +2960,12 @@ pass to word-wide DFFs and address decoders.
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-iattr
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for -attr, ignore case of <value>.
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-rom-only
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only perform conversion for ROMs (memories with no write ports).
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-keepdc
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when mapping ROMs, keep x-bits shared across read ports.
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\end{lstlisting}
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\section{memory\_memx -- emulate vlog sim behavior for mem ports}
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@ -4226,10 +4242,12 @@ Assign names auto-generated from the src attribute to all selected wires and
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cells with private names.
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rename -wire [selection]
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rename -wire [selection] [-suffix <suffix>]
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Assign auto-generated names based on the wires they drive to all selected
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cells with private names. Ignores cells driving privatly named wires.
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By default, the cell is named after the wire with the cell type as suffix.
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The -suffix option can be used to set the suffix to the given string instead.
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rename -enumerate [-pattern <pattern>] [selection]
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@ -5988,6 +6006,9 @@ This command runs synthesis for Cologne Chip AG GateMate FPGAs.
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-nomx8, -nomx4
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do not use CC_MX{8,4} multiplexer cells in output netlist.
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-luttree
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use new LUT tree mapping approach (EXPERIMENTAL).
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-dff
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run 'abc' with -dff option
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@ -6067,7 +6088,11 @@ The following commands are executed by this synthesis command:
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techmap -map +/gatemate/mux_map.v
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map_luts:
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abc -dress -lut 4
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abc -genlib +/gatemate/lut_tree_cells.genlib (with -luttree)
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techmap -map +/gatemate/lut_tree_map.v (with -luttree)
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gatemate_foldinv (with -luttree)
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techmap -map +/gatemate/inv_map.v (with -luttree)
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abc -dress -lut 4 (without -luttree)
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clean
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map_cells:
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@ -7901,6 +7926,9 @@ Import options:
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-v, -vv
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Verbose log messages. (-vv is even more verbose than -v.)
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-pp <filename>
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Pretty print design after elaboration to specified file.
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The following additional import options are useful for debugging the Verific
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bindings (for Yosys and/or Verific developers):
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@ -7941,50 +7969,6 @@ Pretty print options:
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Save output for VHDL design units.
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verific -app <application>..
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Execute YosysHQ formal application on loaded Verilog files.
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Application options:
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-module <module>
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Run formal application only on specified module.
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-blacklist <filename[:lineno]>
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Do not run application on modules from files that match the filename
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or filename and line number if provided in such format.
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Parameter can also contain comma separated list of file locations.
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-blfile <file>
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Do not run application on locations specified in file, they can
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represent filename or filename and location in file.
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Applications:
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WARNING: Applications only available in commercial build.
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verific -template <name> <top_module>..
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Generate template for specified top module of loaded design.
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Template options:
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-out
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Specifies output file for generated template, by default output is stdout
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-chparam name value
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Generate template using this parameter value. Otherwise default parameter
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values will be used for templat generate functionality. This option
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can be specified multiple times to override multiple parameters.
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String values must be passed in double quotes (").
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Templates:
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WARNING: Templates only available in commercial build.
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verific -cfg [<name> [<value>]]
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Get/set Verific runtime flags.
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