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186 Commits

Author SHA1 Message Date
Eddie Hung 72ce06909e Trim mismatched connection to be same (smallest) size 2019-09-20 17:51:36 -07:00
Eddie Hung 567e5f0aa7 Fix first testcase in #1391 2019-09-20 17:51:27 -07:00
Clifford Wolf b76fac3ac3 Add techmap_autopurge attribute, fixes #1381 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-19 20:00:52 +02:00
Marcin Kościelnicki a82e8df7d3 techmap: Add support for extracting init values of ports 2019-09-07 16:30:43 +02:00
Clifford Wolf 30f1ac7ce9 Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-05 13:51:53 +02:00
Clifford Wolf 694a8f75cf Add flatten handling of pre-existing wires as created by interfaces, fixes #1145 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-05 13:30:58 +02:00
Eddie Hung fe61dcce8b Grammar 2019-08-20 20:05:51 -07:00
Eddie Hung 193eae0c84 techmap -max_iter to apply to each module individually 2019-08-20 19:50:20 -07:00
Eddie Hung eae5a6b12c Use ID::keep more liberally too 2019-08-15 14:51:12 -07:00
Eddie Hung 52355f5185 Use more ID::{A,B,Y,blackbox,whitebox} 2019-08-15 14:50:10 -07:00
Eddie Hung 02dead2e60 ID(\\.*) -> ID(.*) 2019-08-15 10:25:54 -07:00
Eddie Hung 78ba8b8574 Transform all "\\*" identifiers into ID() 2019-08-15 10:19:29 -07:00
Eddie Hung 9f98241010 Transform "$.*" to ID("$.*") in passes/techmap 2019-08-15 10:05:08 -07:00
Eddie Hung 4cfefae21e More use of IdString::in() 2019-08-15 09:23:57 -07:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Eddie Hung c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung c2db70f41e Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero 2019-07-09 12:14:00 -07:00
Clifford Wolf e158ea2097 Add log_debug() framework 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 17:25:52 +02:00
Clifford Wolf 7b35d57592 Disable blackbox detection in techmap files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 02:07:36 +02:00
Clifford Wolf f3ad8d680a Add "techmap -wb", use in formal flows 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 11:23:24 +02:00
Clifford Wolf b7445ef387 Check blackbox attribute in techmap/simplemap 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 11:10:05 +02:00
Eddie Hung 290a798cec Ignore 'whitebox' attr in flatten with "-wb" option 2019-04-18 10:32:00 -07:00
Clifford Wolf f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Clifford Wolf a74f805ba0 Fix handling of src attributes in flatten 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 13:55:30 +01:00
Clifford Wolf a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Jason Lowdermilk 8dc6083de7 updated to use get_src_attribute() and set_src_attribute(). 2017-08-31 14:51:56 -06:00
Jason Lowdermilk 32c0f1193e Add support for source line tracking through synthesis phase 2017-08-29 14:46:35 -06:00
Clifford Wolf b3bc7068d1 Fix handling of empty cell port assignments (i.e. ignore them) 2017-07-21 19:32:31 +02:00
Clifford Wolf cf25dc9ce7 Copy attributes to _TECHMAP_REPLACE_ cells 2017-02-16 12:28:42 +01:00
Clifford Wolf db7314bc02 Fix techmap for inout ports connected to inout ports 2017-02-13 16:55:25 +01:00
Clifford Wolf 74702b04c2 Build fixes for VS 2015 2016-10-16 20:37:02 +02:00
Clifford Wolf ffbb4e992e Added MEMID handling to "flatten" pass 2016-10-14 10:36:37 +02:00
Clifford Wolf d8ad889594 Bugfix in techmap parameter handling 2016-09-14 20:46:54 +02:00
Clifford Wolf aadca148da Fixed preservation of important attributes in techmap 2016-05-06 13:59:30 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf 6fe48cf41e equiv_purge bugfix, using SigChunk in Yosys namespace 2015-10-24 19:09:45 +02:00
Clifford Wolf eb1e3caae7 Fixed "flatten" for unconnected inout ports 2015-10-13 10:30:23 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf 3860c9a9f2 Fixed flatten $meminit handling 2015-07-30 21:43:41 +02:00
Clifford Wolf ad919ae4e3 Fixed techmap processes error msg 2015-07-18 12:16:27 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 9f772eb970 Improved "flatten" handlings of inout ports 2015-05-23 10:14:53 +02:00
Clifford Wolf 49859393bb Improved attributes API and handling of "src" attributes 2015-04-24 22:04:05 +02:00
Clifford Wolf be7b9b34ca techmap code cleanup 2015-04-09 12:02:26 +02:00
Clifford Wolf 21a1cc1b60 Added support for "file names with blanks" 2015-04-08 12:14:34 +02:00
Clifford Wolf aa0ab975b9 Removed "techmap -share_map" (use "-map +/filename" instead) 2015-04-08 12:13:53 +02:00
Clifford Wolf 3fe18c26cd Added "keep_hierarchy" attribute 2015-02-25 12:46:00 +01:00
Clifford Wolf 49dd9c713f Fixed "flatten" for non-pre-derived modules 2015-02-21 15:01:13 +01:00
Clifford Wolf f778a4081c Catch constants assigned to cell outputs in "flatten" 2015-02-21 11:21:28 +01:00
Clifford Wolf 8658eed52a Added support for memories to flatten (techmap) 2015-01-17 20:46:52 +01:00
Clifford Wolf 9065fb25cc Fixed handling of foo.__TECHMAP_... 2015-01-15 13:36:57 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf 4aa9fbbf3f Improvements in simplemap api, added $ne $nex $eq $eqx support 2014-12-24 10:49:24 +01:00
Clifford Wolf 546e8b5fe7 Improved TopoSort determinism 2014-11-07 15:21:03 +01:00
Clifford Wolf bbd808072b Added format __attribute__ to stringf() 2014-10-10 17:22:08 +02:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf 7e156a5419 Fixed techmap_wrap for techmap_celltype 2014-09-14 15:34:36 +02:00
Clifford Wolf 124e759280 Added techmap_wrap attribute 2014-09-14 14:49:26 +02:00
Clifford Wolf c50b841b29 Added 'techmap_maccmap' techmap attribute 2014-09-07 18:23:37 +02:00
Clifford Wolf 826fdb34d8 Added "techmap -autoproc" 2014-09-01 15:36:29 +02:00
Clifford Wolf c642dd0b3e Only call proc_share_dirname() in techmap when necessary 2014-08-23 15:32:00 +02:00
Clifford Wolf 19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf 410d043dd8 Renamed toposort.h to utils.h 2014-08-17 00:55:35 +02:00
Clifford Wolf ca87116449 More idstring sort_by_* helpers and fixed tpl ordering in techmap 2014-08-15 02:40:46 +02:00
Clifford Wolf d320e75087 document "techmap -map %<design-name>" 2014-08-15 02:01:30 +02:00
Clifford Wolf 014a41fcf3 Implemented recursive techmap 2014-08-03 12:40:43 +02:00
Clifford Wolf 08ec33a5e5 Implemented simplemap support for "techmap -extern" 2014-08-02 21:55:13 +02:00
Clifford Wolf b6acbc82e6 Bugfix in "techmap -extern" 2014-08-02 20:54:30 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf 768eb846c4 More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf bd74ed7da4 Replaced sha1 implementation 2014-08-01 19:01:10 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf 6ca0c569d9 Added "techmap -assert" 2014-07-31 02:21:41 +02:00
Clifford Wolf 2541489105 Added techmap CONSTMAP feature 2014-07-30 22:04:30 +02:00
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf 8b0f50792c Added techmap -extern 2014-07-27 21:31:18 +02:00
Clifford Wolf 5da343b7de Added topological sorting to techmap 2014-07-27 16:43:39 +02:00
Clifford Wolf 49f72421d5 Using new obj iterator API in a few places 2014-07-27 11:32:42 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf 4e802eb7f6 Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
Clifford Wolf 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00