Clifford Wolf
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61412d167f
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Improvements in satgen undef handling
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2013-11-25 16:50:45 +01:00 |
Clifford Wolf
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bd65e67d8a
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Improvements in satgen undef handling
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2013-11-25 15:12:01 +01:00 |
Clifford Wolf
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11e8118589
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Added ezsat vec_const() api
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2013-11-25 15:10:32 +01:00 |
Clifford Wolf
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8c3f4b3957
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Started implementing undef handling in satgen
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2013-11-25 04:51:33 +01:00 |
Clifford Wolf
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4d43331748
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Removed undef feature from ezsat api
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2013-11-25 02:50:34 +01:00 |
Clifford Wolf
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76f7c10cfc
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Using simplemap mappers from techmap
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2013-11-24 23:31:14 +01:00 |
Clifford Wolf
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3ee33cbdaf
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Added simplemap pass
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2013-11-24 22:52:30 +01:00 |
Clifford Wolf
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1afe6589df
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Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
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2013-11-24 20:44:00 +01:00 |
Clifford Wolf
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8dafecd34d
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Added module->avail_parameters (for advanced techmap features)
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2013-11-24 20:29:07 +01:00 |
Clifford Wolf
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4011d47646
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Added techmap -D and -I options
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2013-11-24 20:04:48 +01:00 |
Clifford Wolf
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7d9a90396d
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Added verilog frontend -ignore_redef option
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2013-11-24 19:57:42 +01:00 |
Clifford Wolf
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20175afd29
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Added "techmap -share_map" option
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2013-11-24 19:50:25 +01:00 |
Clifford Wolf
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019b301541
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Early wire/reg/parameter width calculation in ast/simplify
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2013-11-24 19:40:23 +01:00 |
Clifford Wolf
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620b7c900a
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Updated TODOs
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2013-11-24 17:58:05 +01:00 |
Clifford Wolf
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ae798d3fd5
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Fixed xilinx/example_sim_counter test bench
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2013-11-24 17:55:46 +01:00 |
Clifford Wolf
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41205afc39
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Added proper dumping of signed/unsigned parameters to verilog backend
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2013-11-24 17:47:22 +01:00 |
Clifford Wolf
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0ef22c7609
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Added support for signed parameters in ilang
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2013-11-24 17:37:27 +01:00 |
Clifford Wolf
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7eaad2218d
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Removed now obsolete test cases
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2013-11-24 17:30:04 +01:00 |
Clifford Wolf
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f71e27dbf1
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Remove auto_wire framework (smarter than the verilog standard)
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2013-11-24 17:29:11 +01:00 |
Clifford Wolf
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609caa23b5
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
Clifford Wolf
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1e6836933d
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Added modelsim support to autotest
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2013-11-24 15:10:43 +01:00 |
Clifford Wolf
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72b35e0b99
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Fixed "flatten" top-module detection: Only use on fully selected designs
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2013-11-24 14:10:46 +01:00 |
Clifford Wolf
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981677cf09
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Fixed "make install" dependencies
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2013-11-24 05:05:50 +01:00 |
Clifford Wolf
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28093d9dd2
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Added "top" attribute to mark top module in hierarchy
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2013-11-24 05:03:43 +01:00 |
Clifford Wolf
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a4edecb0ca
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Updated command-reference-manual.tex
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2013-11-23 20:09:47 +01:00 |
Clifford Wolf
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db8ce0fe95
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AppNote 010 typo fixes and corrections
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2013-11-23 20:04:51 +01:00 |
Clifford Wolf
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e216e0e291
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AppNote 010 progress
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2013-11-23 18:52:41 +01:00 |
Clifford Wolf
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5f9c7fc6ea
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Improved handling of techmap special wires
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2013-11-23 16:49:58 +01:00 |
Clifford Wolf
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1de12e1efc
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Improved handling of initialized registers
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2013-11-23 16:26:59 +01:00 |
Clifford Wolf
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532091afcb
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Added more generic _TECHMAP_ wire mechanism to techmap pass
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2013-11-23 15:58:06 +01:00 |
Clifford Wolf
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9ab850e45e
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Making prograss on Appnote 010
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2013-11-23 05:46:51 +01:00 |
Clifford Wolf
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3c023054bc
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Progress on AppNote 010
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2013-11-22 19:08:29 +01:00 |
Clifford Wolf
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bf501b9ba3
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Started to write on AppNote 010: Verilog to BLIF
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2013-11-22 17:33:59 +01:00 |
Clifford Wolf
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7b9ca46f8d
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Updated command-reference-manual.tex
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2013-11-22 15:02:40 +01:00 |
Clifford Wolf
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295e352ba6
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Renamed "placeholder" to "blackbox"
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2013-11-22 15:01:12 +01:00 |
Clifford Wolf
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c854ad2e7e
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Some driver changes/fixes
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2013-11-22 14:53:57 +01:00 |
Clifford Wolf
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a362fd81ae
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Fixed O(n^2) performance bug in verilog preprocessor
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2013-11-22 14:08:43 +01:00 |
Clifford Wolf
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058ceda6a0
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Added more performance measurement infrastructure
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2013-11-22 14:08:10 +01:00 |
Clifford Wolf
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e4429c480e
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Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
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2013-11-22 12:46:02 +01:00 |
Clifford Wolf
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18d003254c
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Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
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2013-11-22 04:41:20 +01:00 |
Clifford Wolf
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8e58bb330d
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Added SigBit struct and refactored RTLIL::SigSpec::extract
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2013-11-22 04:07:13 +01:00 |
Clifford Wolf
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7b01ba384f
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Improved make rules for profiling and debugging
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2013-11-22 04:05:30 +01:00 |
Clifford Wolf
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1c4a6411af
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Updated abc
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2013-11-21 22:39:10 +01:00 |
Clifford Wolf
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40d9542647
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Implemented $_DFFSR_ expression generator in verilog backend
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2013-11-21 21:52:30 +01:00 |
Clifford Wolf
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95c94a02fc
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Fixed async proc detection in mem2reg
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2013-11-21 21:26:56 +01:00 |
Clifford Wolf
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09471846c5
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Major improvements in mem2reg and added "init" sync rules
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2013-11-21 13:49:00 +01:00 |
Clifford Wolf
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84ced2bb8e
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Fixed a bug in "add -global_input"
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2013-11-21 03:01:20 +01:00 |
Clifford Wolf
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64a5f8f75e
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Added "proc_arst -global_arst" feature
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2013-11-20 21:00:43 +01:00 |
Clifford Wolf
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08ceb3729e
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Fixed ilang parser: memory width
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2013-11-20 19:55:52 +01:00 |
Clifford Wolf
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2279b2a196
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Added "add" command (only wires for now)
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2013-11-20 19:37:40 +01:00 |