Commit Graph

1479 Commits

Author SHA1 Message Date
Udi Finkelstein 7ed0e23e19 We can now handle array slices (e.g. $size(x[1]) etc. ) 2020-09-17 00:55:17 +03:00
Udi Finkelstein 6de7ba02e3 Fixed comments, removed debug message 2020-09-16 10:57:06 +03:00
Udi Finkelstein b548722bee Added $high(), $low(), $left(), $right() 2020-09-15 20:49:52 +03:00
Miodrag Milanovic 3f27a4ea68 Use latest verific 2020-09-02 10:22:25 +02:00
clairexen a10893072b
Merge pull request #2352 from zachjs/const-func-localparam
Allow localparams in constant functions
2020-09-01 17:31:48 +02:00
clairexen c1a6097376
Merge pull request #2366 from zachjs/library-format
Simple support for %l format specifier
2020-09-01 17:30:36 +02:00
clairexen 3e1840d036
Merge pull request #2353 from zachjs/top-scope
Module name scope support
2020-09-01 17:30:09 +02:00
clairexen 452442ac2f
Merge pull request #2365 from zachjs/const-arg-loop-split-type
Fix constant args used with function ports split across declarations
2020-09-01 17:28:35 +02:00
Miodrag Milanovic 04d5692a85 Reorder to prevent crash 2020-08-31 12:22:26 +02:00
Miodrag Milanovic 3af499c60f ast recognize lower case x and z and verific gives upper case 2020-08-30 13:33:03 +02:00
Miodrag Milanovic 2f93579bd1 Do not check for 1 and 0 only 2020-08-30 13:15:06 +02:00
Miodrag Milanovic b1e3bc059c Fix import of VHDL enums 2020-08-30 12:25:23 +02:00
Zachary Snow c7ceed3fd3 Simple support for %l format specifier
Yosys doesn't support libraries, so this provides the same behavior as
%m, as some other tools have opted to do.
2020-08-29 13:33:31 -04:00
Zachary Snow ecc5c23b4d Fix constant args used with function ports split across declarations 2020-08-29 13:31:02 -04:00
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
Miodrag Milanovic fe8226a22d Add formal apps and template generators 2020-08-26 10:39:57 +02:00
Zachary Snow 6127f22788 Module name scope support 2020-08-20 20:15:08 -04:00
Zachary Snow 74abc3bbfd Allow localparams in constant functions 2020-08-20 20:10:24 -04:00
clairexen 87b9ee330d
Merge pull request #2122 from PeterCrozier/struct_array2
Support 2D bit arrays in structures. Optimise array indexing.
2020-08-19 17:58:37 +02:00
clairexen 22765ef0a5
Merge pull request #2339 from zachjs/display-format-0s
Allow %0s $display format specifier
2020-08-18 17:39:01 +02:00
clairexen 4aa0dc4dc7
Merge pull request #2338 from zachjs/const-branch-finish
Propagate const_fold through generate blocks and branches
2020-08-18 17:38:07 +02:00
clairexen a9681f4e06
Merge pull request #2317 from zachjs/expand-genblock
Fix generate scoping issues
2020-08-18 17:37:11 +02:00
Claire Wolf 7f767bf2b7 Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-18 17:29:49 +02:00
clairexen 5ee9349647
Merge pull request #2281 from zachjs/const-real
Allow reals as constant function parameters
2020-08-18 17:22:20 +02:00
Zachary Snow 2ee0b8ebea Propagate const_fold through generate blocks and branches 2020-08-09 17:21:08 -04:00
Zachary Snow 96ec9acf84 Allow %0s $display format specifier 2020-08-09 17:19:49 -04:00
Lukasz Dalek ba08c25133 Fix subarray access condition
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 16:16:04 +02:00
Lukasz Dalek 83ddc62034 Rewrite multirange arrays sizes [n] as [n-1:0]
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 14:48:27 +02:00
Zachary Snow c3e95eb1ab Fix generate scoping issues
- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214, resolves #1456
2020-07-31 20:32:47 -06:00
Miodrag Milanovic cc02d58194 Clear last error message 2020-07-29 15:28:33 +02:00
clairexen 45e96d5d87
Merge pull request #2301 from zachjs/for-loop-errors
Clearer for loop error messages
2020-07-28 14:07:26 +02:00
Zachary Snow 58da181af9 Clearer for loop error messages 2020-07-25 10:37:16 -06:00
Zachary Snow f69daf4830 Allow blocks with declarations within constant functions 2020-07-25 10:16:12 -06:00
Zachary Snow 59c4ad8ed3 Avoid generating wires for function args which are constant 2020-07-24 21:18:24 -06:00
Zachary Snow f285f7b769 Allow reals as constant function parameters 2020-07-19 20:27:09 -06:00
Claire Wolf 51ee0b683f Treat all bison warnings as errors in verilog front-end
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:57:31 +02:00
Claire Wolf 7a79843cc3 Use %precedence in verilog_parser.y
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:54:28 +02:00
Claire Wolf 24540291c7 Fix bison warnings for missing %empty
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:50:59 +02:00
Claire Wolf 1f4e452609 Run bison with -Wall for verilog front-end
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:49:36 +02:00
clairexen 021ce8e596
Merge pull request #2257 from antmicro/fix-conflicts
Restore #2203 and #2244 and fix parser conflicts
2020-07-15 11:49:09 +02:00
Kamil Rakoczy 02c071888b Add missing semicolons
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-15 10:15:13 +02:00
Claire Wolf f9ed09423e Add AST_EDGE support to AstNode::detect_latch(), fixes #2241
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-10 18:41:13 +02:00
Kamil Rakoczy d77b3305d8 Fix S/R conflicts
This commit fixes S/R conflicts introduced by commit 6f9be93.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-10 15:03:53 +02:00
Kamil Rakoczy 0ffaddee5e Fix R/R conflicts
This commit fixes R/R conflicts introduced by commit 7e83a51.
Parameter logic is already defined as part of `param_range_type` rule.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-10 15:03:01 +02:00
Kamil Rakoczy de649b9194 Revert "Revert PRs #2203 and #2244."
This reverts commit 9c120b89ac.
2020-07-10 09:59:48 +02:00
whitequark dc35ef05f9 verilog_parser: turn S/R and R/R conflicts into hard errors.
Fixes #2253.
2020-07-09 19:36:59 +00:00
whitequark 9c120b89ac Revert PRs #2203 and #2244.
This reverts commit 7e83a51fc9.
This reverts commit b422f2e4d0.
This reverts commit 7cb56f34b0.
This reverts commit 6f9be939bd.
This reverts commit 76a34dc5f3.
2020-07-09 19:36:32 +00:00
Lukasz Dalek 7e83a51fc9 Support logic typed parameters
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-07-06 09:18:48 +02:00
clairexen 3d8d98d709
Merge pull request #2132 from YosysHQ/eddie/verific_initial
verific: rewrite initial assume/asserts prior to elaboration
2020-07-02 17:50:22 +02:00
clairexen 7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar
Signed and macro grammar update
2020-07-01 16:41:32 +02:00
clairexen 8ce4f8790e
Merge pull request #2179 from splhack/static-cast
Support SystemVerilog Static Cast
2020-07-01 16:40:20 +02:00
clairexen 9d658a1970
Merge pull request #2136 from zachjs/master
Allow constant function calls in for loops and generate if and case
2020-06-30 17:38:49 +02:00
Miodrag Milanovic 561890c4e8 Update verific API version check 2020-06-30 12:13:13 +02:00
Zachary Snow 27cec16cda Allow constant function calls in for loops and generate if and case 2020-06-29 16:06:17 -06:00
Miodrag Milanovic b822beb1b2 Fix crash in verific frontend 2020-06-26 20:11:01 +02:00
Lukasz Dalek 6f9be939bd Parse macro call attached semicolon as empty expression
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-26 15:38:20 +02:00
Lukasz Dalek 7cb56f34b0 Fix integer signing grammar
This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:

parameter integer signed i = 0;
parameter integer unsigned i = 0;

Example of incorrect parameters:

parameter signed integer i = 0;
parameter unsigned integer i = 0;

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-26 15:35:56 +02:00
whitequark 12c016ebdc
Merge pull request #2188 from antmicro/missing-operators
Add logic-assignments operators
2020-06-26 07:30:27 +00:00
whitequark d6bdc09422
Merge pull request #2189 from antmicro/optional-labels
Add support for optional labels
2020-06-26 07:29:24 +00:00
clairexen c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
Kamil Rakoczy 539087f417 Support missing sub-assign and and-assign operators
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 13:29:06 +02:00
Miodrag Milanovic 4aec50a863 optimization, all items should have same attributes 2020-06-25 09:18:53 +02:00
Lukasz Dalek a4b4c22c96 Support missing xor-assign operator
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 14:32:12 +02:00
Lukasz Dalek a8750b496e Support optional labels at the end of package definition
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 11:57:45 +02:00
Lukasz Dalek 3b81a1b809 Support optional labels at the end of module definition
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 11:57:45 +02:00
Kamil Rakoczy 22408f24c7 Add plus-assignment operator
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:54:30 +02:00
Kamil Rakoczy 416a66aee8 Add or-assignment operator
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:53:50 +02:00
Miodrag Milanovic f993d18755 verific - import attributes for net buses as well 2020-06-24 11:01:06 +02:00
Kazuki Sakamoto 429d37ff41 static cast: simplify 2020-06-19 19:09:43 -07:00
Kazuki Sakamoto 185bbbe681 static cast: support changing size and signedness
Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)

Fix #535
2020-06-19 17:39:20 -07:00
whitequark 118e4caa37 Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Anonymous Maarten 504f220619 MSVC does not understand __builtin_unreachable 2020-06-17 15:10:08 +02:00
Anonymous Maarten 35008e6d40 MSVC cannot omit operand in conditional 2020-06-17 15:10:08 +02:00
clairexen b2a0f49371
Merge pull request #2131 from YosysHQ/claire/preserveffs
Do not optimize away FFs in "prep" and Verific front-end
2020-06-10 12:44:23 +02:00
Miodrag Milanovic d6bec3ba1c verific - detect missing memory to prevent crash. 2020-06-10 11:27:44 +02:00
clairexen 5c426d2bff
Merge pull request #2112 from YosysHQ/claire/fix2040
Add latch detection for use_case_method in part-select write
2020-06-09 18:27:59 +02:00
Claire Wolf 3c7122c378 Do not optimize away FFs in "prep" and Verific fron-end
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 15:54:14 +02:00
Peter Crozier f80b09fc58 Support 2D packed bit arrays in struct/union. 2020-06-09 13:52:09 +01:00
Peter Crozier 01ec681373 Support 2D bit arrays in structures. Optimise array indexing. 2020-06-08 20:34:52 +01:00
Peter Crozier 76c499db71 Support packed arrays in struct/union. 2020-06-07 18:33:11 +01:00
Claire Wolf 7ad0c49905 Add latch detection for use_case_method in part-select write, fixes #2040
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 23:25:59 +02:00
clairexen 352731df4e
Merge pull request #2041 from PeterCrozier/struct
Implementation of  SV structs.
2020-06-04 18:26:07 +02:00
Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
abc9: -dff improvements
2020-06-04 08:15:25 -07:00
whitequark 3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-06-04 11:23:06 +00:00
Peter Crozier 0d3f7ea011
Merge branch 'master' into struct 2020-06-03 17:19:28 +01:00
Miodrag Milanovic 71072d1945 Support asymmetric memories for verific frontend 2020-06-01 10:30:03 +02:00
clairexen 0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
ast/simplify: don't bitblast async ROMs declared as `logic`
2020-05-29 16:52:11 +02:00
whitequark 626c74adbd
Merge pull request #2097 from whitequark/ilang_lexer-fix-erange
ilang_lexer: fix check for out of range literal
2020-05-29 09:04:27 +00:00
whitequark 13b2963ded ilang_lexer: fix check for out of range literal.
Commit ca70a104 did not use a correct check.
2020-05-29 06:58:44 +00:00
whitequark 2116d9500c
Merge pull request #2033 from boqwxp/cleanup-verilog-lexer
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-29 06:46:33 +00:00
Rupert Swarbrick 6aa0f72ae9 Silence spurious warning in Verilog lexer when compiling with GCC
The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
2020-05-26 17:54:57 +01:00
Eddie Hung 1ebf7155a7 aiger: cleanup 2020-05-25 08:43:33 -07:00
Eddie Hung c5a9abba11 verilog: move attr from simple_behav_stmt to its children to attach 2020-05-25 07:36:53 -07:00
Eddie Hung 1c117ac023 verilog: do not warn for attributes on null statements 2020-05-25 07:36:53 -07:00
Eddie Hung 88bddb37c9 verilog: handle empty generate statement by removing gen_stmt_or_null...
... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
2020-05-25 07:36:53 -07:00
Eddie Hung d21a07c7b5 verilog: fix #2037 by permitting (and freeing) attributes on null stmt 2020-05-25 07:36:53 -07:00
Eddie Hung 574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
Eddie Hung 38e858af8d
Update frontends/verilog/verilog_parser.y
Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-05-21 09:10:56 -07:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes.
Fixes #2058.
2020-05-19 01:42:40 +02:00