Jannis Harder
587e09d551
Merge pull request #3305 from jix/sva_value_change_logic
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verific: Improve logic generated for SVA value change expressions
2022-05-09 16:40:34 +02:00
Jannis Harder
a855d62b42
verific: Improve logic generated for SVA value change expressions
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The previously generated logic assumed an unconstrained past value in
the initial state and did not handle 'x values. While the current formal
verification flow uses 2-valued logic, SVA value change expressions
require a past value of 'x during the initial state to behave in the
expected way (i.e. to consider both an initial 0 and an initial 1 as
$changed and an initial 1 as $rose and an initial 0 as $fell).
This patch now generates logic that at the same time
a) provides the expected behavior in a 2-valued logic setting, not
depending on any dont-care optimizations, and
b) properly handles 'x values in yosys simulation
2022-05-09 15:04:01 +02:00
Jannis Harder
96f64f4788
verific: Fix conditions of SVAs with explicit clocks within procedures
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For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
2022-05-03 14:13:08 +02:00
Miodrag Milanovic
422db937d4
Ignore merging past ffs that we are not properly merging
2022-04-29 14:35:02 +02:00
Miodrag Milanovic
1cc281ca6f
verific: allow memories to be inferred in loops (vhdl)
2022-04-18 09:10:28 +02:00
N. Engelhardt
57bc29c64a
verific: allow memories to be inferred in loops
2022-04-15 15:10:48 +02:00
Miodrag Milanovic
1a1f529099
Preserve internal wires for external nets
2022-04-01 12:07:15 +02:00
Miodrag Milanovic
bbf65702a1
Fix valgrind tests when using verific
2022-03-30 17:25:53 +02:00
Miodrag Milanovic
703769e494
Properly mark modules imported
2022-03-26 09:43:51 +01:00
Miodrag Milanovic
245ecb0529
Import verific netlist in consistent order
2022-03-25 13:44:16 +01:00
Miodrag Milanovic
29293a57bb
Remove quotes if any from attribute
2022-02-16 19:10:13 +01:00
Miodrag Milanovic
2cef48bf2c
Add ability to override verilog mode for verific -f command
2022-02-09 09:19:25 +01:00
Miodrag Milanovic
0b633b6c2e
Use bmux for NTO1MUX
2022-02-02 16:16:08 +01:00
Claire Xenia Wolf
313340aed5
Add YOSYS to the implicitly defined verilog macros in verific
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-13 18:20:08 +01:00
Miodrag Milanović
2412497c26
Merge pull request #3102 from YosysHQ/claire/enumxz
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Fix verific import of enum values with x and/or z
2021-12-10 19:36:37 +01:00
Claire Xenia Wolf
2da214d721
Fix verific import of enum values with x and/or z
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-10 14:52:27 +01:00
Claire Xen
19773d093f
Update verific.cc
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Ad-hoc fixes/improvements
2021-12-10 14:27:18 +01:00
Miodrag Milanovic
b06f547993
If direction NONE use that from first bit
2021-12-08 11:50:10 +01:00
Miodrag Milanovic
3ebfa3fb84
Make sure cell names are unique for wide operators
2021-12-03 09:49:05 +01:00
Miodrag Milanovic
15a35f5584
No need to alocate more memory than used
2021-11-10 10:50:44 +01:00
Claire Xenia Wolf
2ea757da51
Add "verific -cfg" command
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-11-01 10:41:51 +01:00
Claire Xenia Wolf
83118bfb9e
Fix verific gclk handling for async-load FFs
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-31 17:12:29 +01:00
Miodrag Milanovic
f7cc388bb5
Enable async load dff emit by default in Verific
2021-10-27 15:56:56 +02:00
Miodrag Milanovic
32673edfea
Revert "Compile option for enabling async load verific support"
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This reverts commit b8624ad2ae
.
2021-10-27 15:55:43 +02:00
Miodrag Milanovic
b8624ad2ae
Compile option for enabling async load verific support
2021-10-25 09:04:43 +02:00
Claire Xenia Wolf
90b440f870
Fix verific.cc PRIM_DLATCH handling
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-21 12:13:35 +02:00
Claire Xenia Wolf
16a177560f
Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-21 05:42:47 +02:00
Miodrag Milanovic
17269ae59b
Option to disable verific VHDL support
2021-10-20 10:02:58 +02:00
Miodrag Milanovic
1aa6896966
Support PRIM_BUFIF1 primitive
2021-10-14 13:04:32 +02:00
Claire Xen
2d3c79458d
Merge pull request #3039 from YosysHQ/claire/verific_aldff
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Add support for $aldff flip-flops to verific importer
2021-10-11 10:01:56 +02:00
Claire Xenia Wolf
c8074769b0
Add Verific adffe/dffsre/aldffe FIXMEs
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-11 10:00:20 +02:00
Miodrag Milanovic
93fbc9fba4
Import module attributes from Verific
2021-10-10 10:01:45 +02:00
Claire Xenia Wolf
34f1df8435
Fixes and add comments for open FIXME items
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-08 17:24:45 +02:00
Claire Xenia Wolf
1602a03864
Add support for $aldff flip-flops to verific importer
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-08 16:21:25 +02:00
Miodrag Milanovic
abc5700628
verific set db_infer_set_reset_registers
2021-10-04 16:48:33 +02:00
Miodrag Milanovic
c3d4bb4cc9
update required verific version
2021-09-02 14:59:16 +02:00
Miodrag Milanovic
b59c427348
Make Verific extensions optional
2021-08-20 10:19:04 +02:00
Miodrag Milanovic
be04d8834e
Require latest verific
2021-08-02 10:29:58 +02:00
Miodrag Milanovic
987fca5297
Update to latest verific
2021-07-21 09:46:53 +02:00
Miodrag Milanovic
7a5ac90985
Update to latest Verific with extensions for initial assertions
2021-07-09 09:02:27 +02:00
Miodrag Milanovic
0dbb05a75e
Add additional help
2021-07-05 09:16:54 +02:00
Miodrag Milanovic
c0d8da20d5
Support command files in Verific
2021-06-16 11:21:44 +02:00
Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
Claire Xen
6c56c083f8
Update README
2021-03-04 16:43:30 +01:00
Claire Xen
27d7741540
Merge pull request #2574 from dh73/master
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Accept disable case for SVA liveness properties.
2021-02-15 17:49:11 +01:00
Miodrag Milanovic
13c2fd7137
Ganulate Verific support
2021-02-12 10:08:43 +01:00
Diego H
c96eb2fbd7
Accept disable case for SVA liveness properties.
2021-02-04 15:35:35 -06:00
Miodrag Milanovic
d99c032c27
Require latest Verific build
2021-01-30 09:23:46 +01:00
Claire Xenia Wolf
acad7a6e40
Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-01-20 20:48:10 +01:00
Miodrag Milanovic
1c4a18f66f
Bump required Verific version
2020-12-02 15:18:04 +01:00
Miodrag Milanovic
c228cb74d6
Update verific version
2020-10-30 08:32:59 +01:00
Miodrag Milanovic
c8f052bbe0
extend verific library API for formal apps and generators
2020-10-12 14:56:15 +02:00
Miodrag Milanović
1b7ed719a5
Update required Verific version
2020-10-05 13:27:27 +02:00
Miodrag Milanovic
a44c5df259
use sha1 for parameter list in case if they contain spaces
2020-09-30 09:16:59 +02:00
Miodrag Milanovic
44705102b5
Better error for unsupported SVA sequence
2020-09-18 17:08:00 +02:00
Miodrag Milanovic
3f27a4ea68
Use latest verific
2020-09-02 10:22:25 +02:00
Miodrag Milanovic
04d5692a85
Reorder to prevent crash
2020-08-31 12:22:26 +02:00
Miodrag Milanovic
3af499c60f
ast recognize lower case x and z and verific gives upper case
2020-08-30 13:33:03 +02:00
Miodrag Milanovic
2f93579bd1
Do not check for 1 and 0 only
2020-08-30 13:15:06 +02:00
Miodrag Milanovic
b1e3bc059c
Fix import of VHDL enums
2020-08-30 12:25:23 +02:00
Miodrag Milanovic
fe8226a22d
Add formal apps and template generators
2020-08-26 10:39:57 +02:00
Miodrag Milanovic
cc02d58194
Clear last error message
2020-07-29 15:28:33 +02:00
clairexen
3d8d98d709
Merge pull request #2132 from YosysHQ/eddie/verific_initial
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verific: rewrite initial assume/asserts prior to elaboration
2020-07-02 17:50:22 +02:00
Miodrag Milanovic
561890c4e8
Update verific API version check
2020-06-30 12:13:13 +02:00
Miodrag Milanovic
b822beb1b2
Fix crash in verific frontend
2020-06-26 20:11:01 +02:00
clairexen
c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
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Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
Miodrag Milanovic
4aec50a863
optimization, all items should have same attributes
2020-06-25 09:18:53 +02:00
Miodrag Milanovic
f993d18755
verific - import attributes for net buses as well
2020-06-24 11:01:06 +02:00
whitequark
118e4caa37
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
clairexen
b2a0f49371
Merge pull request #2131 from YosysHQ/claire/preserveffs
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Do not optimize away FFs in "prep" and Verific front-end
2020-06-10 12:44:23 +02:00
Miodrag Milanovic
d6bec3ba1c
verific - detect missing memory to prevent crash.
2020-06-10 11:27:44 +02:00
Claire Wolf
3c7122c378
Do not optimize away FFs in "prep" and Verific fron-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 15:54:14 +02:00
Miodrag Milanovic
71072d1945
Support asymmetric memories for verific frontend
2020-06-01 10:30:03 +02:00
Claire Wolf
fa8cb3e35d
Revert "Add support for non-power-of-two mem chunks in verific importer"
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This reverts commit 173aa27ca5
.
2020-05-17 11:31:11 +02:00
Eddie Hung
39fa1e160d
verific: rewrite initial assume/asserts prior to elaboration
2020-05-15 14:05:28 -07:00
Claire Wolf
173aa27ca5
Add support for non-power-of-two mem chunks in verific importer
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-14 14:38:13 +02:00
Eddie Hung
5017ff4a97
verific: ignore anonymous enums
2020-04-30 07:48:47 -07:00
Eddie Hung
97bfe65d3a
verific: support VHDL enums too
2020-04-27 15:17:13 -07:00
Eddie Hung
dd5f206d9e
verific: recover wiretype/enum attr as part of import_attributes()
2020-04-27 08:43:54 -07:00
Eddie Hung
b52eccef3a
Revert "verific: import enum attributes from verific"
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This reverts commit 5028e17f7d
.
2020-04-24 11:57:55 -07:00
Eddie Hung
d3555c667c
verific: do not assert if wire not found; warn instead
2020-04-23 16:28:11 -07:00
Eddie Hung
5028e17f7d
verific: import enum attributes from verific
2020-04-22 17:26:56 -07:00
Eddie Hung
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
Eddie Hung
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
Claire Wolf
2ce7a0d369
Merge pull request #1667 from YosysHQ/clifford/verificnand
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Add Verific support for OPER_REDUCE_NAND
2020-01-30 19:55:53 +01:00
Claire Wolf
60876ce183
Merge pull request #1503 from YosysHQ/eddie/verific_help
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`verific` pass to print help message when command syntax error
2020-01-30 18:05:16 +01:00
Claire Wolf
23c44afaed
Add Verific support for OPER_REDUCE_NAND
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-30 18:01:13 +01:00
Eddie Hung
f443695a38
Merge remote-tracking branch 'origin/master' into eddie/verific_help
2020-01-27 10:34:10 -08:00
Eddie Hung
d730bba6d2
verific: no help() when no YOSYS_ENABLE_VERIFIC
2020-01-27 10:32:18 -08:00
Eddie Hung
7b445121cc
verific: also unflatten for 'hierarchy' flow as per @cliffordwolf
2020-01-27 10:15:22 -08:00
Eddie Hung
cccc0ae112
verific: unflatten struct ports
2020-01-24 10:12:52 -08:00
Clifford Wolf
22dd9f107c
Send people to symbioticeda.com instead of verific.com
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-12-18 13:06:34 +01:00
Clifford Wolf
db323685a4
Add Verific support for SVA nexttime properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 16:11:56 +01:00
Clifford Wolf
e93e4a7a2c
Improve handling of verific primitives in "verific -import -V" mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 16:00:07 +01:00
Clifford Wolf
6af0d03fae
Add Verific SVA support for "always" properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 15:52:21 +01:00
Clifford Wolf
55bda2b2c6
Correctly treat empty modules as blackboxes in Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-20 12:56:31 +01:00
Clifford Wolf
f6ff311a1d
Do not rename VHDL entities to "entity(impl)" when they are top modules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-20 12:54:10 +01:00
Eddie Hung
e2819ce31c
Oops
2019-11-19 13:25:38 -08:00
Eddie Hung
84711f0e8c
Print help message for verific pass
2019-11-19 13:24:48 -08:00
Clifford Wolf
84982b3083
Improve naming scheme for (VHDL) modules imported from Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 12:13:50 +02:00
Clifford Wolf
d49c6b2cba
Add "verific -L"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 09:14:03 +02:00
Clifford Wolf
4033ff8c2e
Fix handling of "restrict" in Verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-21 12:39:28 +02:00
Clifford Wolf
27d59dc055
Fix erroneous ifndef-NDEBUG in verific.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 14:49:55 +02:00
Clifford Wolf
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
Clifford Wolf
9260e97aa2
Automatically prune init attributes in verific front-end, fixes #1237
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 15:31:49 +02:00
Eddie Hung
c11ad24fd7
Use std::stoi instead of atoi(<str>.c_str())
2019-08-06 16:45:48 -07:00
Eddie Hung
046e1a5214
Use State::S{0,1}
2019-08-06 16:22:47 -07:00
Clifford Wolf
fc462c8243
Call "read_verilog" with -defer from "read"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-29 10:29:36 +02:00
Clifford Wolf
36120fcc30
Only support Symbiotic EDA flavored Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-02 10:14:50 +02:00
Clifford Wolf
2faa1d0e80
Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-30 10:04:26 +02:00
Eddie Hung
c7d7d8ad1b
For hier_tree::Elaborate() also include SV root modules (bind)
2019-05-03 20:53:25 +02:00
Eddie Hung
3ea54ec400
Fix verific_parameters construction, use attribute to mark top netlists
2019-05-03 20:53:25 +02:00
Eddie Hung
a27b42e975
WIP -chparam support for hierarchy when verific
2019-05-03 20:53:25 +02:00
Eddie Hung
0f1a4cc03c
verific_import() changes to avoid ElaborateAll()
2019-05-03 20:53:25 +02:00
Clifford Wolf
7682629b79
Add "read -verific" and "read -noverific"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-27 14:03:35 +01:00
Clifford Wolf
c863796e9f
Fix "verific -extnets" for more complex situations
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 14:17:46 +01:00
Clifford Wolf
cebd21aa96
Merge pull request #858 from YosysHQ/clifford/svalabels
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Add support for using SVA labels in yosys-smtbmc console output
2019-03-09 11:14:57 -08:00
Eddie Hung
ee013fba54
Update help message for -chparam
2019-03-09 01:56:16 +00:00
Eddie Hung
2aa3903757
Add -chparam option to verific command
2019-03-09 01:54:01 +00:00
Eddie Hung
1dc060f32e
Fix spelling
2019-03-09 00:43:50 +00:00
Clifford Wolf
cda37830b0
Add hack for handling SVA labels via Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 10:52:44 -08:00
Clifford Wolf
60e3c38054
Improve "read" error msg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 20:34:42 -08:00
Clifford Wolf
a516b4fb5a
Check if Verific was built with DB_PRESERVE_INITIAL_VALUE
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 19:51:30 +01:00
Clifford Wolf
6d1e7e9403
Remove -m32 Verific eval lib build instructions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-04 15:03:49 +01:00
Clifford Wolf
1eb101a38a
Improve VerificImporter support for writes to asymmetric memories
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-02 15:33:43 +01:00
Clifford Wolf
50b09de033
Fix VerificImporter asymmetric memories error message
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-02 15:05:23 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
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The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Clifford Wolf
3d671630e2
Improve src tagging (using names and attrs) of cells and wires in verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 16:01:22 +01:00
Clifford Wolf
910d94b212
Verific updates
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:21:50 +01:00
Clifford Wolf
5387ccb041
Set Verific flag vhdl_support_variable_slice=1
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-09 21:03:23 +01:00
Clifford Wolf
9850de405a
Improve Verific importer blackbox handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-07 19:48:55 +02:00
Clifford Wolf
4b0448fc2c
Fix compiler warning in verific.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-05 09:26:10 +02:00
Clifford Wolf
5d9d22f66d
Add "verific -L <int>" option
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-04 20:06:10 +02:00
Clifford Wolf
408077769f
Add "verific -work" help message
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-22 17:22:24 +02:00
Clifford Wolf
4b02ee9162
Add Verific -work parameter
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-22 13:30:22 +02:00
Clifford Wolf
e343f3e6d4
Add "verific -set-<severity> <msg_id>.."
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-16 11:49:17 +02:00
Clifford Wolf
0899a53bee
Verific workaround for VIPER ticket 13851
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-16 11:31:19 +02:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override
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Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
Clifford Wolf
e275692e84
Verific: Produce errors for instantiating unknown module
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Because if the unknown module is connected to any constants, Verific will
actually break all constants in the same module, even if they have nothing
to do structurally with that instance of an unknown module.
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 18:44:05 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf
65234d4b24
Fix handling of eventually properties in verific importer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-17 12:43:30 +02:00
Clifford Wolf
5041ed2f7d
Fix verific -vlog-incdir and -vlog-libdir handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-16 18:47:42 +02:00
Clifford Wolf
f897af626d
Fix "read -incdir"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-16 16:48:09 +02:00
Clifford Wolf
f39b897545
Add "read -incdir"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-16 15:32:26 +02:00
Clifford Wolf
8b92ddb9d2
Fix verific eventually handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-29 19:24:58 +02:00
Clifford Wolf
0404cf61d5
Add verific support for eventually properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-29 19:21:04 +02:00